Verilog syntax errors

Question

Near "(": syntax error, unexpected '(', expecting ')'.

I have no idea why I got errors.

//P[0]------------------------------------------ 
//Y[0], A[0], B[0]  
    and32bit and_inst0(.Y(s0), .A(MCND), .B(32{MPLR[1]}));
    and32bit and_inst1(.Y({s1,LO[0]}), .A(MCND), .B(32{MPLR[0]}));
//(Y[0], w[0], A[0], B[0], CI)
    rc_add_32 fa0(.Y({s2,LO[1]}), .CO({s1,co}), .A(s0), .B({s1, LO[0]}), .CI(1'b0));

score 2 · Accepted Answer · answered Apr 24 '15 at 05:52

You have an error in replication operator, i.e. 32{MPLR[1]}. The correct syntax for this operator looks like following:

{n{m}} //Replicate value m, n times

As you can see, there are two {} brackets needed. In your code it would be {32{MPLR[1]}} and {32{MPLR[0]}}.

Verilog syntax errors

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