How to pass parameters to a verilog module when performing synthesis?

Question

I have a parameterized verilog module with a bitwidth that is variable depending on the value given in `define WIDTH.

However, I would like to be able to somehow change the value of WIDTH by passing in a parameter during synthesis using design compiler.

I was wondering if there is a way to do this?

For instance, I'd like to be able to write the following for my input file for design compiler:

analyze -format sverilog -define WIDTH 10 myverilogfile.v

That probably depends on your design compiler, refer to the user manual first. One idea, if that functionality isn't built into the compiler, is to write a small script to substitute a keyword with a value, then run the analyze function. — N8TRO, Mar 29 '15 at 03:42

score 4 · Accepted Answer · answered Mar 30 '15 at 07:23

4

For Design Compiler the format is:

analyze -format sverilog -define WIDTH=10,DEPTH=128 myverilogfile.v

answered Mar 30 '15 at 07:23

Morgan

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What about if I am using parameterized modules? not a defines file – Veridian Nov 07 '15 at 00:27

score 0 · Answer 2 · answered Mar 29 '15 at 17:13

Yes, most compilers will let you do this. It is tool-specific, though, there is no standard spec for this. The most common format to do this would be +define+WIDTH=10; you would have to check the documentation or help for your compiler though (or experiment)

How to pass parameters to a verilog module when performing synthesis?

2 Answers2