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In Verilog, I know we can't pass "events" between modules. Howe about in System Verilog ? I would like the event "trig" hooking the trigger source blocks "eventGen" and is consumed by the block "eventConsume" Some how I get compilation error

Code:

module propagateEvents;

reg clk;
event trig;

initial
begin
    clk = 1'b0;
end

always #10 clk = ~clk;

eventGen eventGen (trig, clk);
eventConsume eventConsume (trig, clk);

endmodule

module eventGen(trigGen, clk);

input clk;
event trigGen;

reg count[3:0];

initial
    count = 0;

always @(posedge clk)
begin
    count = count + 1'b1;
    if (count == 'h8)
        ->trigGen;
end

endmodule

module eventConsume(trigConsume, clk);

input clk;
event trigConsume;

always @(trigConsume)
begin
    $display("Trigger caught");
end
endmodule
Greg
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Mike
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  • I get the error as "Error-[RILIP] Register in low conn of input port propagateEvents.sv, 21 "trigGen" Non-net variable 'trigGen' cannot be an input or inout port. Error-[RILIP] Register in low conn of input port propagateEvents.sv, 40 "trigConsume" Non-net variable 'trigConsume' cannot be an input or inout port. – Mike Feb 25 '15 at 02:59

1 Answers1

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You need to give a port direction; ex. inout event. Working example here. SystemVerilog can also use ref event.

Note that event is not synthesizable. Also reg count[3:0] needs to be reg [3:0] count.

module eventGen(output event trigGen, input clk);
reg [3:0] count;
initial count = 0;
always @(posedge clk)
begin
    count = count + 1'b1;
    if (count == 'h8)
        ->trigGen;
end
endmodule

module eventConsume(input event trigConsume, input clk);
always @(trigConsume)
begin
    $display("Trigger caught");
end
endmodule
Greg
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    No need to use a `ref` port. An event variable used in an assignment to another event passes a handle to the event, which is in itself a reference. Just make the port an `output` to `eventGen` and an `input` to `eventConsume` – dave_59 Feb 25 '15 at 04:17
  • Can we assign event data type to other event data type. I have two or more events, say eventA, eventB, eventC. I would like the "trigConsume" to be eventA | eventB | eventC; in other words assign trgConsume = eventA | eventB | eventC is valid semantically ? – Mike Mar 04 '15 at 23:42
  • `always @(eventA or eventB or enventC) ->trigConsume;` or `always @(eventA) ->trigConsume; always @(eventB) ->trigConsume; always @(eventC) ->trigConsume;`. Doing `trigConsume=eventA`, will alias it to eventA, but `trigConsume=eventB`, will override the alias. `eventA=trigConsume; eventB=trigConsume;` will alias everything. See [IEEE Std 1800-2012](http://standards.ieee.org/getieee/1800/download/1800-2012.pdf) section 6.17 _Event data type_ – Greg Mar 05 '15 at 00:49