Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of fpga and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also: altera

554 questions

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1 answer

Output 'X' instead of '1' or '0' in VHDL

I am working on a code convertor using multiplexors and I am facing issues when testing it on ModelSim. Basically it outputs X where there should output 1. I found out that the error may be where I put others >= '0' as when I changed it to 1; the…

vhdl quartus intel-fpga

asked Mar 09 '23 at 21:00

bestgamer14

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1 answer

How to connect module to module in Verilog?

I am a beginner in the development of FPGA. I am interested in how to correctly combine several modules in the top-level file. For example: in the top-level file, I want to connect the output of module 1 to the input of module 2, and so on. Please…

verilog system-verilog fpga quartus intel-fpga

asked Feb 11 '23 at 09:45

Oleh

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1 answer

Error (10818): Can't infer register because it does not hold its value outside the clock edge, how to fix it?

I have this code for a ram in VHDL and I get the following error while synthesis: Error (10818): Can't infer register for "data_table[19][13]" at RAM.vhd(50) because it does not hold its value outside the clock edge any help would be…

vhdl quartus

asked Jan 22 '23 at 02:26

ARA

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1 answer

SV code: if statement inside always_comb construct does not infer purely combinational logic

I cannot figure out the solution to this error, and the only other answer I find online for the same error is this I have been stuck on this problem for a while and I feel like I am going in circles. I am not sure what I am skipping. The error…

if-statement system-verilog quartus intel-fpga

asked Nov 21 '22 at 21:40

Adam Montano

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1 answer

I wrote this code in Verilog and there are no error messages, but it doesn't work

This is the module: module test (output reg [7:0] Q_out, input [2:0] data_in); always begin case (data_in) 3'b000: Q_out = 8'b10000000; 3'b001: Q_out = 8'b01000000; 3'b010: Q_out = 8'b00100000; 3'b011:…

verilog system-verilog hdl modelsim quartus

asked May 13 '22 at 13:55

gela gela

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1 answer

Swapping 2 parameters in always_ff @

I have an issue with my code. I'm trying to swap between Xspeed and Yspeed at the same clock while the if statement is true. I'm getting the errors: cant resolve multiple constant drivers for net and constant drivers at module_name Several if…

verilog system-verilog quartus

asked Apr 14 '22 at 10:49

Avichay Ashur

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2 answers

I think it is a bug. ModelSim cannot be called from Quartus on Ubuntu

I have Quartus Prime Lite 21.1 installed on Ubuntu 20.04 and it is working fine. I also have ModelSim 20.1.1 and it is working fine I've put the right path to ModelSim on Quartus Prime, and it can even recognize the version (unfortunantly, I'm…

ubuntu modelsim quartus

asked Mar 13 '22 at 01:39

domvito55

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1 answer

Changing triggering edge depending on clock polarity signal

I'm trying to implement some logic that is either triggered on a rising or falling edge of the same clock, depending on a clock polarity signal. I tried the following but got an error message in Quartus 15.1 (error id: 10628): "Can't implement…

vhdl clock edges quartus

asked Jan 18 '22 at 17:58

tobiashellbusch

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2 answers

Verilog HDL syntax error at practice.v(7) near text "or"; expecting ")"

I have changed the setting to the same name as the module. There are no other Verilog files in the folder where this file is stored. I don't know what is wrong with the grammar. module test(A,B,F); input A; input [1:0]B; output F; reg F; always…

syntax-error verilog quartus

asked Jan 16 '22 at 02:04

周志桓

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1 answer

Capturing the right posedge clock in Quartus waveform

I am using Quartus Prime Lite 19.1.0. module memory_address_register1 #( parameter ADDR_WIDTH = 4 )( input clk, rst, load, input [ADDR_WIDTH-1:0] add_in, output reg …

verilog quartus test-bench digital-logic register-transfer-level

asked Dec 25 '21 at 16:09

Blaco

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2 answers

Trying to do frequency scaling of 50 MHz signal to 1MHz with below code. "endmodule" error occurs

module PWM_Gen( input clk, // Clock input input [7:0]DUTY_CYCLE, // Input Duty Cycle output PWM_OUT // Output PWM ); reg [7:0]counter_out; // 8-bit counter always @(posedge clk) begin if (DUTY_CYCLE > counter_out) …

verilog quartus

asked Nov 07 '21 at 14:05

Kunal R

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1 answer

How do I generate N counters inside a generate block to load test an FPGA?

I need to estimate the maximum number of 16-bit counters that a FPGA board can fit. I created a 16-bit counter module with enable (en) and terminal count (TC), and instantiated this inside a generate block in a top level module. However, I need to…

verilog counter xilinx quartus intel-fpga

asked Oct 23 '21 at 05:36

pranav bharadwaj

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1 answer

Beginner's Question on Compiling Verilog in Quartus

I'm in the process of learning Verilog. I am trying to create a code where I get an LED to blink at a certain frequency. I know the clock I am using is 100Mhz, so I wanted it to operate at a cycle of 1Hz. I set a registry for 27 bits, which should…

verilog quartus

asked Oct 19 '21 at 15:10

JTH828

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1 answer

Quartus 20.1 high logic cell usage

I stumbled across a really weird behavior in Quartus Lite Edition. I'm setting up a development container for a university project using the DE2-115 Board with a Cyclone IV FPGA. Using Quartus 19.1 everything builds well and works as expected but if…

fpga quartus intel-fpga

asked Sep 15 '21 at 12:32

Lehrlii

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1 answer

test bench is no working. z and x states in modelsim

i realized a bubble sort code on verilog. there are no any synthesis erorrs, but test bench is not working in modelsim. it shows x and z states module sort #( parameter NUM_VALS = 5, parameter SIZE = 16 )( input wire clk, input …

sorting verilog fpga modelsim quartus

asked Jun 25 '21 at 13:13

dduy_le

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