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Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also:

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is it possible to call out Verilog function in a VHDL code by using Quartus

I'm currently reviewing 2 types of code (VHDL and Verilog). I trying to combine some function from Verilog into VHDL code by using Quartus. Is it possible to do it directly in Quartus? Or any recommend free Verilog2VHDL converter?
Ben Dan
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Tristate buffers in Quartus II

I need to clear up a problem with an external input to a CPLD by putting it through a tristate buffer. I know Quartus II has a tristate-buffer megafunction, but I am curious - if I simply tell it to output Z on the specific pin, will in…
shieldfoss
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VHDL - Usage of high impedance

I started learning VHDL and I'm current following a book instructions that suggested a 4 to 8 multiplexer with buffer. So I decided to build a 4x1 MUX. But I can't figure out how to set an individual output as high impedance. LIBRARY ieee; USE…
Matheusarceu
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VHDL Error(10482) object std_logic_vector is used but not declared

I have written some code about an 8-bit adder using full adders as components. When I start the compilation, it shows one error that I am not able to find. I may have other mistakes that I can't notice. library ieee; use…
Cornelia Parker
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How to add a qip file to a Quartus project generated from a Makefile

I like to have the project file untouched unless I make an active decision to add something, so I create the project file using make. The first instance of the project file is created by quartus_map and I can later add pin declarations etc using…
Bimme
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VHDL allow to pass real (floating point) numbers through ports?

VHDL allow to pass real (floating point) numbers through ports? For this code: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.math_real.all; entity FPP_MULT is port(A : in integer; --input operands B…
osb
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Quartus 18 IP Error

I am currently trying to use Quartus 18.0 IP Catalog suggestions to import a UART RS-232 block to set up this serial interface. I have set the clock domain and the output pin (using datasheet to DE0-CV board) but when I try to finish the UART setup…
Roman Kishmar
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How to initialize an output in verilog?

I have been trying to initialize my output LEDR [3:0] to all 0. However, LEDR keeps being XXXX in my waveform timing diagram. I have tried using initial block, but it doesn't work. (My IDE is Quartus Prime) Here is my code module…
W.Joe
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Altera design library does not contain primary unit

I am using following altera 2008 library: library altera_2008; use altera_2008.fixed_generic_pkg.all; When running the Quartus 17.1 compiler I get following error message: Error (10481): VHDL Use Clause error at Polyfit.vhd(48): design library…
Norick
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Object is used but not declared

I understand this is a fairly common question. Regardless, having gone through forums, I couldn't find a satisfactory answer as to why I'm getting the following CT error, for the given VHDL code. Can you help me please? VHDL Code library IEEE; use…
cappy0704
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VHDL "Process": Incorrect usage of process?

I'm brand new to VHDL and the Quartus design environment, and I'm trying to run the simulation of some textio but I must be missing something... When I compile the following code (which I borrowed snippets of from an OSU VHDL textio guide…
jakedaly
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How to check for "ZZZZ" input in VHDL?

I have a in std_logic_vector(3 downto 0) and a out std_logic_vector(6 downto 0). With a process and case, I am checking all possible binary conditions such as when "0000" => output_var <= "1111111"; and so on. My program works for all specified…
Robert C. Holland
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Error (10818): Can't infer register because it does not hold its value outside the clock edge

I have been trying to implement an asynchronous counter, and the simulations are correct, but I keep on getting this error from Quartus Error (10818): Can't infer register for "encoderCounta[0]" at EncoderComputation.vhd(35) because it does not…
Amira
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How to use Tcl/Tk with VHDL

I am new to both VHDL and Tcl/Tk. Straight to question: I want to know how to use Tcl/Tk in Modelsim. Suppose I do not know anything in Tcl/Tk, but I have the following VHDL code for a full adder to start with. What can I do with it using Tcl/Tk…
SimonMatt
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VHDL : for loop, index arithmetic doesn't work

I'm trying to set up a simple bruteforce convolution processor with my DE0 Nano Altera FPGA board. Here's what my code looks like : LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_bit.all; ENTITY Convolution IS PORT( clock : IN…
ricothebrol
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