Quartus 20.1 high logic cell usage

Question

I stumbled across a really weird behavior in Quartus Lite Edition. I'm setting up a development container for a university project using the DE2-115 Board with a Cyclone IV FPGA.

Using Quartus 19.1 everything builds well and works as expected but if I use version 20.1 I saw that the fitter takes 17 minutes instead of 8 seconds.

What catched my eye, when comparing the logs, is that the used resources increased from 18897 to 118824 logic cells, but the RAM Segments were reduced from 322 to 190. The higher amount of resources is probably the reason why the fitting and routing process takes 17 minutes.

Did anybody ran into a comparable behavior ? Is there something I should activate/deactivate?

Synthesis log ouput Quartus 19.1

...
[0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 745 ps
[0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:07
[0m[0;32mInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst"
[0m[0;32m    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
[0m[0;32mInfo (21057): Implemented 19285 device resources after synthesis - the final resource count might be different
[0m[0;32m    Info (21058): Implemented 6 input pins
[0m[0;32m    Info (21059): Implemented 35 output pins
[0m[0;32m    Info (21060): Implemented 16 bidirectional pins
[0m[0;32m    Info (21061): Implemented 18897 logic cells
[0m[0;32m    Info (21064): Implemented 322 RAM segments
[0m[0;32m    Info (21065): Implemented 1 PLLs
[0m[0;32m    Info (21062): Implemented 8 DSP elements
[0m[0;32mInfo: Quartus Prime Analysis & Synthesis was successful. 0 errors, 33 warnings
[0m[0;32m    Info: Peak virtual memory: 1337 megabytes
[0m[0;32m    Info: Processing ended: Wed Sep 15 08:32:55 2021
[0m[0;32m    Info: Elapsed time: 00:01:04
[0m[0;32m    Info: Total CPU time (on all processors): 00:01:13
...

Synthesis log ouput Quartus 20.1

...
[0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 330 ps
[0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:27
[0m[0;32mInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst"
[0m[0;32m    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
[0m[0;32mInfo (21057): Implemented 119080 device resources after synthesis - the final resource count might be different
[0m[0;32m    Info (21058): Implemented 6 input pins
[0m[0;32m    Info (21059): Implemented 35 output pins
[0m[0;32m    Info (21060): Implemented 16 bidirectional pins
[0m[0;32m    Info (21061): Implemented 118824 logic cells
[0m[0;32m    Info (21064): Implemented 190 RAM segments
[0m[0;32m    Info (21065): Implemented 1 PLLs
[0m[0;32m    Info (21062): Implemented 8 DSP elements
[0m[0;32mInfo: Quartus Prime Analysis & Synthesis was successful. 0 errors, 25 warnings
[0m[0;32m    Info: Peak virtual memory: 1181 megabytes
[0m[0;32m    Info: Processing ended: Wed Sep 15 09:49:49 2021
[0m[0;32m    Info: Elapsed time: 00:02:48
[0m[0;32m    Info: Total CPU time (on all processors): 00:02:57
...

Full logs:

https://github.com/t-crest/patmos/files/7169188/build_log_quartus_20.1.log

https://github.com/t-crest/patmos/files/7169189/build_log_quartus_19.1.log

Answer 1

I notice that in the 20.1 log, it says the following (in bold) a bunch of times:

Info (125068): Revision "patmos" was previously opened in Quartus Prime software version 19.1.0 Lite Edition. Created Quartus Prime Default Settings File /opt/t-crest/patmos/hardware/quartus/altde2-115/patmos_assignment_defaults.qdf, which contains the default assignment setting information from Quartus Prime software version 19.1.0 Lite Edition.

Info (125069): Default assignment values were changed in the current version of the Quartus Prime software -- changes to default assignments values are contained in file /opt/intel_FPGA/quartus/linux64/assignment_defaults.qdf

You might want to compare in your .qsf file what these default settings that were changed are, since maybe that accounts for some change in how the logic is being inferred.

More specifically, what catches my eye in the log is that in the 20.1 version, it says this:

Info (276014): Found 12 instances of uninferred RAM logic

Along with a lot of statements about asynchronous reads:

Info (276007): RAM logic "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_4:tagMem|mem" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 6420

However, those aren't present in the 19.1 log. Instead, the 19.1 log lists a bunch of altsyncram megafuntions with synchronous RAM logic that aren't present in the 20.1 log.

Info (276029): Inferred altsyncram megafunction from the following design logic: "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_4:tagMem|mem_rtl_0"

So that seems like the likely culprit for the discrepancy. Try to figure out why the RAMs are being inferred differently, or the origin/constraints of the signal that the 20.1 version believes is asynchronous.