Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of fpga and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also: altera

554 questions

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Basic Verilog Circuit Questions

I'm trying to write a basic circuit in Verilog using Quartus Prime as a side project for a professor. That said, I'm having trouble with Verilog syntax. The circuit that I want to make is a collection of AND and OR gates that theoretically determine…

verilog hdl quartus

asked Nov 27 '18 at 19:04

bpryan

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am trying to make code in verilog Quartus for 8-bit 2x1 MUX but i have errors in the code

module muxx(M, X, Y, S, SW,LEDR,LEDG) ( input [17:0]X, input [17:0]Y, output [15:0]LEDR, output [7:0]LEDG, output [7:0]M ); if S=0; M=X; while if S=1; M=Y; wire [7:0] X = SW[7:0]; wire [7:0] Y = SW[15:8]; wire S = SW[17]; input…

verilog quartus

asked Oct 16 '18 at 17:17

Ali Mahmmud

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How to correctly slice an array of real numbers in SystemVerilog?

Quartus returns this error: "and indexing x returns an aggregate value". The code: module splineInterp(x, y); input real x [64:0][0:4]; output real y; y = x[1] - x[0]; endmodule

system-verilog quartus

asked Sep 24 '18 at 18:14

Санат Б

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Module instantiation inside main module

Obligatory: I'm new to Verilog. I have two individual, working verilog modules: a nios-ii ADC and a counter module. The nios-ii controlled ADC qsys is properly instantiated in the main module. I am trying to instantiate the counter inside the main…

verilog quartus

asked Jun 14 '18 at 21:47

Cup-0-Joe

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1 answer

Stuck on assigning parts of an array to a number in Verilog

input [31:0] instruction; output [4:0] read_reg_1; read_reg_1 <= instruction[6:10]; I want to assign array elements 6 to 10(6-7-8-9-10) as 5 bit numbers of read_reg_1 Error (10170): Verilog HDL syntax error at mips_fetch.v(8) near text "<="; …

arrays verilog quartus

asked Nov 16 '17 at 20:02

stacknotflow

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Verilog Increment Decrement counter using Altera Board

Hey so I'm basically brand new to Verilog and not quite sure how the syntax works and things like this. The assignment is as below Use a push button and a switch on the Altera board to increment or decrement a 4 bit counter. The value of the…

verilog counter intel-fpga quartus digital-design

asked Oct 02 '17 at 15:58

Lucas Wetherall

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3 answers

How to wait for edges in always block?

I am trying to write something like this: always@(posedge bus_start) begin @(posedge scl) buffer[7] = sda; @(posedge scl) buffer[6] = sda; @(posedge scl) buffer[5] = sda; @(posedge scl) buffer[4] = sda; @(posedge scl) buffer[3] =…

verilog fpga quartus

asked Jun 06 '17 at 08:18

J.Z

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Verilog code with wrong waveform (Mutliplier Circuit)

module multiplication (multiplier, multiplicand, product, clk); input [3:0] multiplier; input [4:0] multiplicand; input clk; output [7:0] product; reg [7:0] product; initial begin product [7:4] = 4'b0000; product [3:0] =…

verilog quartus

asked Dec 09 '16 at 10:31

Ambitions

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How to use the input's values in "always" definiton in Verilog

I got the problem with using the input's value in Verilog. I write: module reg_vector (INPUT, ICLK, IENBL, NR, OUT); parameter k = 6; parameter n = 3; input [(8*k)-1:0] INPUT; input ICLK; input IENBL; input [n-1:0] NR; reg [n-1:0] temp; output reg…

verilog quartus

asked Nov 08 '16 at 16:48

Андрей Боровилов

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1 answer

I've made a design in Quartus-II (modelsim), now I want to pass it to the board (I request ORIENTATION)?

once again I request your orientation. I have successfully designed a circuit in verilog trough Quartus-II and Modelsim, Details: Basically it's a (kinda complex) arithmetic circuit based on binary fixed point arithmetic using a FSM (in order to…

verilog fpga synthesis quartus

asked Oct 27 '16 at 11:59

sujeto1

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1 answer

Altera UART IP Core

I am trying to make some tests with an FPGA and while trying to add an UART to my design using the Quartus II v13.0 SP1 and the Megawizard plug-in I realised that there is no UART available there but it is available from Qsys tool. My question is…

fpga uart intel-fpga quartus qsys

asked Jun 17 '15 at 08:05

osuarez

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2 answers

Why is this variable not considered a constant?

The following is code I wrote is a test bench to simulate a decoder (Verilog HDL). It converts [15:0]IR to [25:0]ControlWord. Literal is a byproduct that is watched as well. All values from 0-65535 need to be tested for the 16-bit IR variable. In…

loops iteration verilog hdl quartus

asked Apr 26 '15 at 04:10

user3571270

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1 answer

full adder with two half adder in quartus ii

I am new in quartus. one of my home work was to implement a full adder with two half adder in quartus. now I created half adder but I don't know how to use it in other schematic file to implement full adder. thanks.

quartus

asked Mar 18 '15 at 09:36

user4684540

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How can I improve my ad hoc cruise control system for Nios 2?

I have written in Nios 2 an ad hoc cruise control system for a school assignment. I versioned it with github. We want the cruise control to differ at most 2 m/s for speeds >= 25 m/s. The latest improvement I could do was checking the velocities in…

c embedded nios quartus ucos

asked Mar 11 '15 at 01:33

Niklas Rosencrantz

25,640
75
229
424

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Simulation blinking LED using VHDL with Quartus II and ModelSim

I'm new to VHDL, Quartus II and ModelSim. Now I'm doing a lab where we are constructing a blinking LED. How should simulation be handled when the construction deals with relatively long time periods. The frequency of the blinking LED is 1 Hz and the…

vhdl quartus

asked Oct 25 '14 at 20:14

Alexander

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