Verilog HDL syntax error at practice.v(7) near text "or"; expecting ")"

Question

I have changed the setting to the same name as the module. There are no other Verilog files in the folder where this file is stored. I don't know what is wrong with the grammar.

module test(A,B,F);
input A;
input [1:0]B;
output F;
reg F;
always @(*)
    if({A,B}==3'b001 or {A,B}==3'b010 or {A,B}==3'b100 or {A,B}==3'b101)
        F=1;
    else F=0;
endmodule 

Answer 1

or is a legal keyword in Verilog, but it can not be used in that context. It can be used as a built-in primitive OR gate, or in a sensitivity list.

You likely want it to behave as the logical OR operator, in which case you would use || instead:

if({A,B}==3'b001 || {A,B}==3'b010 || {A,B}==3'b100 || {A,B}==3'b101)

Alternately, you could enable SystemVerilog features in your tools and use the set membership inside operator:

module test(A,B,F);
input A;
input [1:0]B;
output F;

assign F = ({A,B} inside {3'b001, 3'b010, 3'b100, 3'b101});

endmodule 

This code is simpler to understand, and it scales better since it is easier to add/remove a comparison value.

Answer 2

The logical OR operator in Verilog is ||, not or.