How do I generate N counters inside a generate block to load test an FPGA?

Question

I need to estimate the maximum number of 16-bit counters that a FPGA board can fit. I created a 16-bit counter module with enable (en) and terminal count (TC), and instantiated this inside a generate block in a top level module. However, I need to generate these counters in a chain where the TC output of one acts as the enable for the next counter in the chain. I'm unable to figure out the logic for this. Can anyone help me ?

16-bit counter code:

module counter_16 (clk, Q, TC, en);

input clk, en;
output [15:0] Q;
output TC;

wire clk, en;
reg [15:0] Q = 0; //initial value for the output count
reg TC;

always @(posedge clk)
begin
    if(en == 1)
    begin
        Q <= Q+1;
    end
    TC = &Q; //TC is 1 when all bits of Q is high
end

endmodule

Counter generation module:

module counter_generator
#(
    parameter n = 10
)
(output [15:0] cnt_out,
output TC,
input clk, en);

wire [n-1:0] temp_en;
temp_en[0] <= 0;
wire [15:0] temp_out;

generate 
    genvar i;
    for(i=1;i<=n;i=i+1)
    begin : counter_identifier
        counter_16 counter_16_gen (
        .clk(clk), 
        .Q(temp_out), 
        .TC(temp_en[i-1]), 
        .en(en));
    end
endgenerate 
endmodule

toolic · Answer 1 · 2021-10-23T12:23:50.950

The first thing to do is make the loop start from 0, not 1, so that the signal indexes align.

Create a signal tc_out that is n bits wide and connect that directly to the TC port in the generate block, using the index [i]. TC of instance 0 is connected to tc_out[0], etc. This is straightforward, and it helps us with the en connections.

Create a signal temp_en that is also n bits wide and connect that directly to the en port in the generate block. The key is to assign this signal to the tc_out signal as seen below.

en of instance 0 is driven by the en input of counter_generator
en of instance 1 is driven by the TC output of instance 0
en of instance 2 is driven by the TC output of instance 1
etc.

Lastly, create an array of n 16-bit wires, temp_out, and connect that directly to the Q port in the generate block.

module counter_generator
#(
    parameter n = 10
)
(
output [15:0] cnt_out,
output TC,
input clk, en
);

  wire [n-1:0] tc_out;
  wire [n-1:0] temp_en = {tc_out[n-2:0], en};
  wire [15:0]  temp_out [n];
  assign TC = temp_out[n-1];

generate 
  genvar i;
  for (i=0; i<n; i=i+1) begin : counter_identifier
        counter_16 counter_16_gen (
          .clk  (clk), 
          .Q    (temp_out[i]),
          .TC   (tc_out  [i]), 
          .en   (temp_en [i])
        );
  end
endgenerate 
endmodule

How do I generate N counters inside a generate block to load test an FPGA?

1 Answers1