Trying to do frequency scaling of 50 MHz signal to 1MHz with below code. "endmodule" error occurs

Question

module PWM_Gen(

input clk,             // Clock input
input [7:0]DUTY_CYCLE, // Input Duty Cycle
output PWM_OUT         // Output PWM
);

reg [7:0]counter_out; // 8-bit counter

always @(posedge clk)   
begin
   if (DUTY_CYCLE > counter_out)
   PWM_OUT = 1;
   else
   PWM_OUT = 0;
end

counter counter_inst (  
    .clk(clk),
    .counter_out(counter_out)
)

endmodule

error is -

Error (10170): Verilog HDL syntax error at PWM_Gen.v(51) near text: "endmodule"; expecting ";".

For the compile issue --> Please declare counter_out as wire. Use wire [7:0] counter_out and add a semicolon after in the closing bracket of the counter_inst i.e. /*Previous code*/ .counter_out(counter_out) ) ; //Here add semicolon — Pradyuman Bissa, Nov 08 '21 at 04:52

score 2 · Answer 1 · edited Oct 11 '22 at 16:33

2

It's a typo. You need a ; after the counter_inst instantiation:

counter counter_inst (   
    .clk(clk),
    .counter_out(counter_out)
);

edited Oct 11 '22 at 16:33

toolic

57,801
17
75
117

answered Nov 07 '21 at 14:30

Dario Petrillo

980
7
15

score -1 · Answer 2 · answered Oct 11 '22 at 16:27

-1

It should be added after the counter_inst instantiation, means ; after the ).

answered Oct 11 '22 at 16:27

Anish Kumar

1

Trying to do frequency scaling of 50 MHz signal to 1MHz with below code. "endmodule" error occurs

2 Answers2