Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of fpga and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also: altera

554 questions

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Issues Regarding Quartus Synthesis Running Time

I am running Quartus II 13.0sp1 (64-bit) Web Edition. I used to design my modules in ModelSim simulator. Unfortunately, when I tried to test my program using the Altera Kit via Quartus II 13.0sp1. It takes so long time to run the program. Beside the…

vhdl fpga modelsim intel-fpga quartus

asked Feb 18 '14 at 22:06

user3300910

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Is there a way to make Quartus II to support PAL devices?

I use in school the Galaxy to write and compile VHDL programs, but it only runs on Windows XP and I don't have it. I installed Quartus II in my computer (I use Ubuntu), but apparently there is no support for PAL devices (specifically GAL22V10D). It…

vhdl hdl intel-fpga quartus

asked Jan 28 '14 at 01:26

Adrian

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1 answer

Why is my 8-bit counter stuck at 0 or 255?

I am trying to write some simple Verilog code for practice reasons. I am using the FPGA Cyclone 4. My 8-bit counter works fine with the on-board clock (50MHz), but it's way too fast to see the LEDs at that speed, so I tried first to slow the clock…

verilog counter quartus 8-bit cyclone

asked Apr 14 '23 at 14:20

johnny_1010

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votes

1 answer

How to eliminate the logic gate and the adder

The logic gate in the RTL view was a latch previously. As an answer suggests, I assign each input with outputs. And the latch turns into a logic gate. I don't know whether it is a correct way to solve the problem. There is also an adder connected to…

vhdl quartus register-transfer-level

asked Nov 22 '22 at 12:49

RoseLegend

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2 answers

How to drive outputs in Verilog

I am trying to implement I2C in a FPGA to learn verilog, i am a complete beginner and am having trouble with an error: Error (10028): Can't resolve multiple constant drivers for net "rComStarted" at I2CModule.v(14) I am currently just trying to…

verilog fpga i2c quartus

asked Sep 23 '22 at 18:34

Tzanker

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1 answer

Couldn`t design the timer in VHDL properly

I have only started with the FPGA and I have a problem. I need the counter to activate only after the logical state of input srab equals to 1. However the statement seems to ignor it. After uploading the program to the FPGA ALTERA Cyclone IV leds…

vhdl fpga quartus

asked Aug 12 '22 at 06:18

NewbieN

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1 answer

VHDL count and shift

8-bit input value is transferred from Data to A when load is 1. And when S becomes 1, if A(0) is 1, the value of B is increased by 1, and A is shift right. When the value of A becomes 00000000, we make done 1 and escape. Therefore, the number of 1's…

vhdl quartus

asked Mar 28 '22 at 13:33

Phil

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2 answers

How to prevent inferred latch and latch unsafe behavior in Verilog?

I am having trouble with a specific part of my program, here in the always block: module compare_block (clk, reset_n, result, led); parameter data_width = 8; //width of data input including sign bit parameter size = 1024; input…

verilog system-verilog quartus

asked Aug 11 '20 at 16:41

Tarashi99

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1 answer

Can parameters be variable

I know that we can use parameters to make generic modules, and to improve readability of code. My question is whether we can have these parameters themselves as a variable. Something like this: module parameterModule #(parameter p1, ...)(); …

verilog hdl quartus iverilog icarus

asked Jul 16 '20 at 03:11

Akilesh Kannan

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1 answer

Assign leds to register output (verilog)

How to assign (phisicaly) leds to [8-bit] register output, i mean module reg4 ( input [4:0] key, output [4:0] led ); wire clk; wire [4:1] d = ~ key [4:1]; global g (.in (~ key [0]), .out (clk)); reg [4:1] q; always @(posedge clk) q <=…

verilog quartus

asked Mar 16 '18 at 17:26

demsp

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1 answer

Verilog HDL syntax error near text “for”; expecting “endmodule”

module alu(input logic [31:0] a, b, input logic [2:0] f, output logic [31:0] y, output logic zero); wire [31:0] ANDed, ORed, SLT, sum, cout, bn; wire set_less; reg zero_detect; genvar i; …

verilog quartus

asked Mar 13 '18 at 04:08

Eddy Mejia

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