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Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also:

554 questions
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System Verilog Error , GPIO_0 is not a function

I have a module like this module DE1_SoC (CLOCK_50, HEX0, HEX1, HEX2, HEX3, SW, GPIO, KEY); input CLOCK_50; // 50MHz clock. output reg [6:0] HEX0; output reg [6:0] HEX1; output reg [6:0] HEX2; output reg [6:0] HEX3; inout…
Big_t boy
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How to get a rgb picture into FPGA most efficiently, using verilog

I am trying to write a verilog code for FPGA programming where I will implement a VGA application. I use Quartus II and Altera DE2. At the moment, my aim is to get a 640x480 rgb image during compilation (method doesn't matter as long as it works…
ozgeneral
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Quartus: VHDL Error 10430

Getting some strange errors when I try to compile my code onto my DE2 board using Quartus. My friend has tried my code on his computer and it compiles without error, however on mine, it gives me the following errors. Info: Running Quartus II 64-Bit…
user4907284
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QuartusII 14.1.0 Debian Linux crash

I can't use Quartus 14.1.0 with Linux Debian (wheezy and Jessie) on my 64 bits computer. If I launch it on console I've got this message : user@fpgaformation:/opt/altera/14.1/quartus/bin$ ./quartus Inconsistency detected by ld.so: dl-close.c: 743:…
FabienM
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Does Quartus II support line.all?

I implemented some VHDL code to exports FSM state encodings at compile time, which can be read back by Xilinx ChipScope. This functionality is tested with Xilinx ISE 14.7, iSim 14.7 and Mentor Graphic's QuestaSim 10.2c. My design can be synthesized…
Paebbels
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When I try to open a project, Quartus opens and then closes itself

I'm not fully sure why this is happening. I also think it's important to say that this is only happening for one of my specific projects. I am still able to open other perfectly.
StoneMan
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Shifting and adding a std_logic_vector (has 36 but must have 18 elements)

I'm facing some weird errors from quartus when I try this. Here's the code (all the unsigned & other weird functions was my attempt at persuading Quartus to compile it.) library ieee; use ieee.std_logic_1164.all; use…
MightyPork
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Prevent compiler from optimizing logic away

I'd like to generate a reset signal (active high) that will last for a short period of time. I achieved it by following code: always @(posedge clk or negedge rst_n or posedge data) begin if(~rst_n | data) data <= 1'b0; else if(ena) data…
Qiu
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Quartus Programmer II TCL flash *.pof file

Is there a script to upload a *.pof file using TCL Scripting through Quartus Programmer on my FPGA? Preferably from the command line because i want integrate it into my custom software.
Antonio
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Why doesn't the simplest example work (VHDL, Quartus)?

Here is my VHDL code: entity test is port ( x1, x2 : in bit; f : out bit ); end test; architecture behavior of test is begin f <= x1 and x2; end behavior; In Quartus (v. 18.1) I go to File->New->University Program…
Vladimir Korshunov
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How can I stop the simulation at stop bit for I2C master code?

I am trying to write Verilog code for I2C master, and there are a couple of problems I am facing. I was able to compile and run its testbench on Quartus and modelsim, respectively. However, I am trying to have it switch back to reset mode on (reset…
Qazi Zabeer
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The RTL viewer in Quartus is omitting redundant gates

I have written Verilog code for 2 back to back not gates. However, when I pull up the RTL in the RTL viewer, the back to back not gates are not shown; instead, a wire is shown. I am using Intel Quartus Lite 22.1 RTL view: My Code: module…
Bhawesh Mishra
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Reset a simple counter

I'm trying to write a simple counter using Verilog on Quartus Prime and a testbench in Verilog being tested with Questa FPGA modelSim. The goal of my counter is to count up to 7 at positive edge of a clock cycle and wrap back to 0 after 7 or if the…
Reeve Prinson Fernandes
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Variable does not update in module

I'm trying to write a simple Verilog module and a testbench for it on intel's Quartus Prime and checkout it's waveform on Questa FPGA simulator. The code basically has a clock and a 4-bit counter. The counter should increment at every positive edge…
Reeve Prinson Fernandes
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$readmemh syntax error for .mif file in Verilog HDL Intel Quartus Prime

I am trying to read a .mif file and this is the error I am getting - Error (10170): Verilog HDL syntax error at sine3_test1.MIF near text: p. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel…
Maverick
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