Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of fpga and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also: altera

554 questions

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3 answers

VHDL testbench for a device that uses two previously defined and tested entities

Warning: this is going to be long. Sorry if it's too verbose. I'm just starting out on learning FPGAs and VHDL using Quartus Prime. Over the past few days I've taught myself: How to write VHDL How to make a component How to write a testbench How…

vhdl quartus test-bench

asked Jul 04 '18 at 11:02

DiBosco

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1 answer

Finite state machine VHDL reset

I am new to VHDL and I have a question about the implementation of a FSM. I would like the behaviour shown in the picture (where I implemented the same FSM with AHDL). When I implement it in VHDL I have a different behaviour of the reset : if it…

vhdl hdl state-machine quartus

asked May 20 '17 at 15:34

AM93

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1 answer

ModelSim does not compile overloaded functions and undefined range types

I'm running ModelSim 10.3d, and I have this code in a package: package core_params_types is type array_1d_logic is array (natural range <>) of std_logic; type array_1d_logic_vector is array (natural range <>) of std_logic_vector (natural range…

vhdl overloading modelsim intel-fpga quartus

asked Feb 04 '16 at 01:41

Raul

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2 answers

VHDL - Testbench internal signals

I am spending some time learning about writing test benches to try out on some of the models I have produced. Does anyone know a way to monitor signals that are internal to the architecture of the unit under test. I have tried using LIBRARY…

vhdl modelsim quartus

asked Feb 03 '16 at 23:12

hoboBob

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1 answer

Should be 1.001 us equal to 1001 ns in VHDL?

I'm currently writing a test to check whether the type time is synthesized / simulated properly in various FPGA vendor tools. One corner case is the usage of real literals as the abstract literal for time values, e.g.: 1.001 us. The IEEE Std.…

vhdl xilinx-ise quartus vivado

asked Jan 11 '16 at 17:32

Martin Zabel

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1 answer

Issue with parameters in Modelsim

Recently I've came across following issue: in Quartus software I've defined my Verilog module as follows: module module_name( input [w1-1:0] in1, input [w2-1:0] in2, output [w1-1:0] out1 ); parameter w1 = 16; parameter…

verilog modelsim quartus

asked Oct 19 '15 at 16:07

Qiu

5,651
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56

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2 answers

Extracting Memory Initialization File (MIF) from a BMP photo

I am working on the DE12-115 microprocessor from Altera using Quartus. In order to display a BMP image onto a monitor using the built-in VGA connections, I must first transform the BMP image into its MIF Format. The MIF format will be nothing but a…

java c intel-fpga quartus cyclone

asked Apr 25 '15 at 07:06

TheLebDev

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2 answers

What happens when there are multiple architectures on a single entity?

Suppose one has an entity which has two architectures defined. Those two architectures work with the same entity (obviously) and subsequently the two set the output pins to different values. My question is, how does the program (simulator) determine…

compilation vhdl modelsim quartus

asked Apr 13 '15 at 20:20

nettek

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2 answers

Compiling *.vhdl into a library, using Altera Quartus II

I am trying to use 'Floating point and Fixed point package' as a part of my filter design in VHDL. I am using Altera Quartus II as the development environment. I downloaded the file package from the website: http://www.vhdl.org/fphdl/, now available…

floating-point vhdl fixed-point intel-fpga quartus

asked Oct 25 '13 at 02:38

ElectroJunkie

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3 answers

Failed to load .sof file to Cyclone II fpga board

I am new to VHDL and FPGA. I have written a sample code which does EXOR of a and b and stores it in c. This code is in VHDL behavioral architecture. I am using Quartus 11.1+SP2-2.11. I assigned pins say a to SW0, b to SW1 and c to LEDG0. Everything…

vhdl fpga quartus

asked Sep 27 '13 at 01:28

San

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1 answer

Attempting to make a signal high for 5 clock cycles and then remain low

I am trying to make the signal called ld_tx_data_scope a value of 1 after the first 5 positive edges and remain high for 5 positive edges, and then have it go low and stay low. However, simulating the Verilog code provides this output for…

verilog system-verilog quartus

asked Jun 02 '23 at 23:29

programmer25

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1 answer

In Intel Quartus, can I initialize RAM using a string parameter?

I need to initialize several instances of the same ram module with different data files which I would like to do as follows: module ram #( string HEXFILE = "split1.mem" ) ( input logic clk, input logic [31:0] a, input logic [7:0] …

verilog system-verilog fpga quartus intel-fpga

asked Dec 04 '21 at 03:39

Plasty Grove

2,807
5
31
42

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2 answers

Error: syntax error in set_input_delay (Quartus)

The Fmax parameter in my code was reported as : No Paths to report. Therefore, I was trying to set input signal relationship with the defined clock using set_input_delay. However, the error report states: Verilog HDL Syntax error near text "-" ;…

syntax-error verilog quartus

asked Aug 08 '20 at 14:20

Vatsala Prasad

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1 answer

Where would a GND driver come from?

Please help me with this error in quartus. I cannot figure out where the GND driver is coming from. ERROR: The node "filter|input_val[7] has multiple drivers. "non-tri-state driver "filter|input_val[7]$latch" " is one of the multiple drivers".…

verilog system-verilog quartus

asked Jul 31 '20 at 15:48

Tarashi99

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2 answers

Quartus does not allow using a Generate block in Verilog

Pretty simple problem. Given the following code: module main( output reg [1:0][DATA_WIDTH-1:0] dOut, input wire [1:0][DATA_WIDTH-1:0] dIn, input wire [1:0][ADDR_WIDTH-1:0] addr, input wire [1:0] wren, input wire clk ); …

verilog fpga hdl quartus intel-fpga

asked Jun 02 '20 at 15:09

Kraken

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