Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of fpga and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also: altera

554 questions

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I want to type conversion in Quartus2 Verilog

I want to type conversion in Quartus2 Verilog....... integer to reg ex) integer a = 10; reg[3:0] b; $cast(b,a); but $cast is not supported synthesis..

verilog quartus

asked Jun 08 '21 at 16:53

chundeuk

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2 answers

Error: 12014 - I can't link priority circuit module with seven segment module

So below is my priority circuit module module prm (input logic D, A, E, F, output logic [3:0] y); always_comb if (D) y = 4'b1000; else if (A) y …

module compiler-errors verilog system-verilog quartus

asked Apr 20 '21 at 17:29

Courier_6

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1 answer

Does Quartus support in-memory synthesis?

I'm working on a project that generates a large number of components. I'm having the problem that Quartus is generating an extremely large number of files in the /db directory, on the order of hundreds of thousands. The system I am working on has…

quartus intel-fpga

asked Apr 19 '21 at 18:29

Heiko

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0 answers

Problem with using division operator in Quartus using VHDL

We need to divide two integers using VHDL and run on FPGA. Below is the the code we wrote for integer addition and it compile in the Quartus but when we try to compile the division code it gave error as "Error (10327): VHDL error at…

vhdl division quartus intel-fpga nios

asked Apr 07 '21 at 05:38

Dilum Bandara Wijesundara

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1 answer

What am I doing wrong? Testbench not updating correctly

I am trying to implement the testbench so that after 3 ticks, each input gets the new specified valued. For example, first 3 seconds (or ticks) A = 10, B = 0, and then the next 3 seconds (3 seconds to 6 seconds) A = 10, B = 16 and etc. However, on…

verilog fpga quartus intel-fpga

asked Mar 18 '21 at 21:15

RhinoECE

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1 answer

Quartus crashes when trying to synthesize RAM in Verilog

I am trying to do VGA RAMDAC at Altera MAX II (EPM240). I am create 76800 bytes array for RAM. The hvsync_generator module generates a VGA signal. The main module takes data from RAM and transfers it to the pixels bus. It works well, pixels (320 *…

verilog fpga quartus synthesis

asked Mar 12 '21 at 18:14

RedSpirit

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0 answers

Intel Quartus Error 12002 Port does not exist in macrofunction

Working with an Intel Cyclone 10 FPGA and running into a compile error I cannot seem to debug properly. The errors I get are: Error (12002): Port "out_msg" does not exist in macrofunction "inst6" Error (12002): Port "msg" does not exist in…

vhdl intel fpga can-bus quartus

asked Jan 06 '21 at 14:55

user29091

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1 answer

How to change pin voltage in quartus ii?

I'm trying to change pin voltage on 'Altera cyclone 4 FPGA' in Quartus? I have changed it in a pin planner and source voltage. But, unfortunately, the voltmeter always show '3 - 3.3 V'. Am I missing something. Please, advise.

fpga quartus

asked Dec 16 '20 at 05:38

Kendra_T

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1 answer

A low logic level turn on LEDs and high logic level turn off LEDs in quartus with Altera Cyclone FPGA

I have a development board with an EP4CE6E22C8 FPGA. And I have the following verilog code in Quartus Prime: module Test(out); output [7:0] out; assign out = 8'b00111100; endmodule The pin planner has been configured as pointed by the schematic.…

fpga quartus intel-fpga

asked Dec 09 '20 at 22:38

RdlP

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Quartus netlist optimization lost register fanout in a state machine

Hi guys i'm trying to implement a state machine but i have the problem that during timing simulation i get an error saying that Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below. Info: Register…

vhdl state-machine quartus

asked Nov 25 '20 at 17:17

JohanB

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1 answer

Verilog self checking testbench will not run? Building a simple ALU, this shouldn't be so hard

I am tasked with building an ALU. However, I must not understand how the testbench should run. I have run other simple testbenches just fine. code compiles (using quartus) made a text file and turned it into a "test.tv" file opened modelsim and…

verilog system-verilog hdl modelsim quartus

asked Sep 11 '20 at 19:55

Preston

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1 answer

Prevent sharing of adder logic

Suppose the following VHDL component: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder is port ( iClk : in std_logic; iDataA : in unsigned(7 downto 0); iDataB : in unsigned(7 downto…

vhdl quartus synthesis

asked Aug 17 '20 at 15:03

sebi707

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1 answer

Can't resolve multiple constant drivers for net Quartus error

The errors I received were: 10028 Can't resolve multiple constant drivers for "led" at compare_block.sv (66) 10029 Constant driver at compare_block.sv(61) What are the multiple constant drivers here? Originally, I had the led assignment (led <=…

verilog system-verilog quartus

asked Aug 01 '20 at 22:54

Tarashi99

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1 answer

FPGA to HPS communication in VHDL with FIFO

I am trying to realize a communication between my FPGA and the HPS on the Altera DE10nano development board. To edit the vhdl i use the Quartus Prime software. While the communication is working in general (as in i can get some data form the fpga to…

vhdl fpga quartus

asked Jun 30 '20 at 10:28

user13840042

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1 answer

Quartus RTL viewer parameter is not synchronous with VHDL code. Error (10344) VHDL

I'm doing my project by referring to "https://github.com/eigenpi/Face-Detection-on-FPGA"'s project. I planning to change the OV7670 camera to Terasic-D5M camera. I try to change the input parameter bits from 8 bits to 12 bits but it shows error…

vhdl fpga face-detection quartus

asked Jun 10 '20 at 19:55

Ben Dan

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