SV code: if statement inside always_comb construct does not infer purely combinational logic

Question

I cannot figure out the solution to this error, and the only other answer I find online for the same error is this I have been stuck on this problem for a while and I feel like I am going in circles. I am not sure what I am skipping. The error points toward the line with the first if statement. What I am trying to achieve in my code is a mode select where mode 1 will display certain information, and mode0 will display different information on an fpga.

module modesel(input logic mode, clk, reset, 
                    input logic [6:0] LOAD,
                    input logic [7:0] pc, ac, state, mdr, opcode, value, address,
                    output logic [9:0] LEDR,
                    output logic [7:0] left, middle, right);
    
            up3(.clk(clk), .reset(reset), .store_mem(LOAD[0]), .fetch(LOAD[1]), .load_pc(LOAD[3]), .incr_pc(LOAD[2]), .load_iru(LOAD[5]), .load_irl(LOAD[4]), .load_ac(LOAD[6]), 
                      .pc(pc), .ac(ac), .state(state), .mdr(mdr), .opcode(opcode), .value(value), .address(address));
            
               always_comb
            
                if (mode==1) begin//mode1   
                    LEDR[6:0] = LOAD[6:0];
                    LEDR[8:7] = 0;
                    LEDR[9] = 1;
                    left = pc;
                    middle = address;
                    right = mdr;
                    
                end
            
                else if(mode==0) begin//mode0
                    case(state)
                        8'h00: LEDR[7:0] = 8'b0000_0000;
                        8'h01: LEDR[7:0] = 8'b0000_0001;
                        8'h02: LEDR[7:0] = 8'b0000_0010;
                        8'h03: LEDR[7:0] = 8'b0000_0100;
                        8'h04: LEDR[7:0] = 8'b0000_1000;
                        8'h05: LEDR[7:0] = 8'b0001_0000;
                        8'h06: LEDR[7:0] = 8'b0010_0000;
                        8'h07: LEDR[7:0] = 8'b0100_0000;
                        8'h08: LEDR[7:0] = 8'b1000_0010;
                        default: LEDR[7:0] = 8'b0000_0000;
                    endcase
                    LEDR[9:8] = 0;
                    left = opcode;
                    middle = value;
                    right = ac;
                    
                end
                
endmodule

I have been able to keep up so far, but whenever I run into a problem like this it is difficult to solve on my own.

I have tried multiple things like adding assign statements outside the always_comb block, and other suggestions from the previous post I linked above, but I am met with more errors. Any help is appreciated.

The up3 module ports are:

module up3(input logic clk, reset, 
            output logic store_mem, fetch, load_pc, incr_pc, load_iru, load_irl, load_ac,
            output logic [7:0] pc, ac, state, mdr, opcode, value, address);

The exact error message that I receive is:

Error (10166): SystemVerilog RTL Coding error at modesel.sv(16): always_comb construct does not infer purely combinational logic.

I should add that this module is meant to be called in my testbench for programming my DE0CV FPGA board. The test bench code is:

module up3tb(input logic [3:0] KEY,
             output logic [9:0] LEDR,
             output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5);    

logic [6:0] LOAD;
logic [7:0] PC, AC, STA, MDR, OPC, VAL, ADR, L, M, R;


 modesel test( .mode(KEY[3]), .clk(KEY[0]), .reset(KEY[1]), 
                    .LOAD(LOAD[6:0]),
                    .pc(PC), .ac(AC), .state(STA), .mdr(MDR), .opcode(OPC), .value(VAL), .address(ADR),
                    .LEDR(LEDR[9:0]),
                    .left(L), .middle(M), .right(R));
                    
                
            dual_seg7 L_out(.blank(0), .test(0), .data(L), .segments1(HEX5), .segments2(HEX4));//Left, PC or Opcode
            dual_seg7 M_out(.blank(0), .test(0), .data(M), .segments1(HEX3), .segments2(HEX2));//Middle, Address or Value
            dual_seg7 R_out(.blank(0), .test(0), .data(R), .segments1(HEX1), .segments2(HEX0));//RIght, AC or MDR
            
            
endmodule

toolic · Answer 1 · 2022-11-21T22:29:51.130

When I try to compile your code on another simulator (VCS), I get many messages like:

Error-[VIPCBD] Variable input ports cannot be driven
  Variable input ports cannot be driven.
  The input variable port "LOAD" of module "modesel" is connected to output 
  port "store_mem" of module "up3".
  up3 i0( .clk (clk),  .reset (reset),  .store_mem (LOAD[0]),  
  .fetch (LOAD[1]),  .load_pc (LOAD[3]),  .incr_pc (LOAD[2]),  .load_iru 
  (LOAD[5]),  .load_irl (LOA ...

You should not drive the inputs of the modesel module (within the modsel module) with outputs of the up3 module. Perhaps up3 should be outside the modsel module.

Also, I had to give up3 an instance a name: i0

module up3tb ...
    ...
    modsel test ( ... );
    up3    i0   ( ... );
endmodule

SV code: if statement inside always_comb construct does not infer purely combinational logic

1 Answers1