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Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also:

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VHDL - Quartus II modsim

I'm starting to write a VGA controller for a DE0 board. I have a model which compiles and loads onto the DE0 board. Also it displays the test message. The problem I am having is I cannot simulate my controller using Quartus II modsim. When I run the…
hoboBob
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Simulation of Modelsim launching from Quartus doesn't work properly

This is the test bench `timescale 1 ps/ 1 ps module sum_fix_vlg_tst(); reg select; reg [7:-8] valor_a; reg [7:-8] valor_b; // wires wire [8:-8] result_fx; sum_fix i1…
sujeto1
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Using a non-constant value inside "while", gives me this error, what can I do?

I'm trying to make addition and subtraction of floating point. My guide is a book "Computer Arithmetic and Verilog HDL Fundamentals" by Cavanagh. Inside the module he use a code for aligning exponents as I show as follows. always @ (oper_1 or…
sujeto1
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VHDL constants returning 10500 error in quartus II

I need to initialize a number of constants for seven segment display uses, but I am having some issues with them. Whenever I compile constant displayR : type := b"01010000"; I get Error (10500): VHDL syntax error at VendingMachine.vhd(62) near…
deef0000dragon1
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Warning about missing signal in VHDL process sensitivity list

I'm currently designing a simple multiple input SPI master in Quartus. Given it is a serial protocol, I have a serial clock and a signal that stores the current bit index. One of the processes I have written looks like this: store_bits :…
M Schubert
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VHDL Vending machine with an error in port map

I'm doing a vending machine project, the only problem I have is the port map for Seg where I get this error: Warning: COMP96_0411: reu.vhd : (363, 31): Actual of mode 'out' cannot be assigned to formal "x" of mode 'in'. Error: COMP96_0100: reu.vhd…
DNA5511
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Conversion of 8-bit binary number to decimal number for 7 segment decoder

I am currently a beginner programming to an FPGA board in VHDL using Quartus II. I need to convert an 8 bit number of type std_logic_vector to three separate 4 bit std_logic_vector variables so that i may display a decimal number on three 7 segment…
coolKoala
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object notation in verilog

I am newbie to verilog hdl. For testing a single cycle mips cpu, I am trying to use the following notation to initialize a register from the testbench. CPU.IM.memory[i] = 32'b0 Here, CPU is one module which has a declaration for IM (another…
Saurabh
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How to use/declare an unsigned Integer value in VHDL?

I'm trying to design a basic Vending machine on a Altera DE1-SoC Board. My question comes from trying to code the State Machine that will control the vending process. How do you track the $ value being added jumping between states? I think the…
VKkaps
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hexadecimal seven segment display verilog

I've taken a project using verilog. We have two 4-bits number, a multiplexer(S0,S1) and four module(adder,substractor,and,xor). Output is 4 bit. I think it seems simple alu. I have written a verilog code that contains all of them as modules. I have…
user4134614
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Multiple Interrupt Senders in one peripheral in Qsys

Using Qsys (Quartus II x64 15.0.1 build 150) I made a system with Nios2/e and several standard peripheral components. I also add my custom component with 1 MM-Slave and 2 Interrupt Senders. For each of them I set this slave as "Associated…
Mishka
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Variable or signal in vhdl for shared value between different process

I need to share a value (a real) between two process, but when I try to run my code, quartus gives me an error. library IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; use…
Federico Ponti
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Simulating INOUT port with Modelsim (VHDL)

Im trying to simulate a RAM memory with Quartus and Modelsim by Altera. The problem is that when i assing values to data_inout in the test bench and simulate, the wave is always in 'U' state. It doesnt take any value when i do data_inout <=…
rockstiff
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Timing specifications for LCD module

I'm writing a VHDL code for a TFT LCD 7" screen by terasic and I'm having a hard time understand the timing specifications presented in the datasheet page 17, table 3-1 in manual (download-link) page 15, section 8.3 in datasheet…
Doron Behar
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Loop naming in SystemVerilog with Quartus

Quartus requires loop naming, even if SystemVerilog does not. Is there a way to avoid it? (I could use ModelSim, but I need Quartus for my FPGA.)
marvell
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