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Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also:

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Calculate fmax of Altera design

After I finished my design compilation on Quartus, I get multiple result for fmax as shown below. I want to know, what does it means? and How can I calculate the fmax of the all design?. My design is implementation for the following equation: for(i…
abdelhamedia
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Send a bitstream in an FPGA board

I need to be able to send bitstream in a FPGA board. I use the Altera Cyclone III Development Board, I am looking for an option on Quartus for example to send bitstream, but I didn't find this either in the software nor on Internet.
Gilstaills
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LATCH Primitive disables outputs?

So I understand the concept of a latch, but I'm not seeing how I am inferring one here as my else condition should cover all the possible paths through this process. Quartus is telling me it is disabling the greenLEDS and redLEDs because of LATCH…
user4907284
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Having FPGA to output sound on "line out" pin using verilog

I am trying to write a verilog code for FPGA which will output sound from the embedded "line out" pin. I use Quartus II and Altera DE1. I am new to hardware programming, therefore it just takes too much time for me to catch up with basics.…
ozgeneral
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Verilog error expecting a description

module controle(clock, reset, funct, opcode, overflow, PCW, PCCondW, PCDataW, PCSrc, EPCW, AluOutW, MemRegW, AluOp, AluSrcA, AluSrcB, BShift, BSrc, ShamtSrc, AW, RegW, RegDst, RegSrc, Loads, Stores, IRW, MemW, IorD, LSE); input [5:0] opcode,…
Caio Jose
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How to connect my clockDivider into this verilog program with Quartus II

Code: TestBench.v: // ============================================================ // // Traffic light tester module. // // We clock the device as usual, supply reset, and eventually "push // the walk button" to activate the traffic light. // //…
avgvstvs
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Floating point numbers in Quartus II

I am designing a FIR filter in Verilog with Quartus II. I need floats for my coefficients so I tried using float however reall is not supported by Quartus so what do I do? Thanks
George Waller
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Simple Quartus compiling error related to device restrictions

I have a relatively simple circuit that I'm trying to compile. It requires 491 I/O pins, so I'm selecting a non-default device that has more than 456 (Cyclone IV GX with 508 user I/Os). The problem is that when compiling I receive this…
Gaspa79
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VHDL signal's Delay - Quartus

I faced a problem when using Quartus II from Altera. In the VHDL course, I have a problem about the behavior of VHDL variables VS signals. The theory says that the VHDL variables get its new value immediately. On the other hand , the signal's…
Heba
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What's wrong with this VHDL code - BCD Counter?

I'm studying VHDL right now, and I have a pretty simple homework assignment - I need to build a synchronous BCD counter that will count from 0 to 9 and when it reaches 9, will go back to 0. I wanted to experiment a little so I decided not to do the…
nettek
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VHDL & Synthesizing w/Quartus simple error

So I'm currently trying to synthesize a design and apparently it's too big to compile or something. It compiles and simulates perfectly in ModelSim, but in quartus throws this error: Error: Design requires 491 I/O resources -- too many to fit in…
Gaspa79
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What's wrong with this simple VHDL for loop?

For some reason the OutputTmp variable will always be uninitialized in the simulation. I can make it work without a for loop but I really want to automate it so I can later move on to bigger vectors. The intermediate variable works fine. Note: I'm a…
Gaspa79
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Is setting signal values to unitialized acceptable?

To achieve something in my VHDL code I'm currently doing: tmpOutput <= "UUUUUUUU"; Is that seen as something wrong entirely? Also, can this bring problems when synthesizing the design? Thanks a lot!
Gaspa79
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Waveform file not running under simulation

When I click under the button Run functional Simulation, I see this error: Determining the location of the ModelSim executable... Using: C:\altera\13.1\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options ->…
Marcela Yanza
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16 bit adder using 2 bit adder as component

I am trying to create a 16-bit adder using 2-bit adders as components (which themselves use 1-bit adder as component). However, my code doesn't compile in Quartus II. Can someone help me please? Thank you very much! My project is consisted of 3…
elChino
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