I am currently a beginner programming to an FPGA board in VHDL using Quartus II. I need to convert an 8 bit number of type std_logic_vector
to three separate 4 bit std_logic_vector
variables so that i may display a decimal number on three 7 segment displays (the largest number in that will be dealt with is 254). currently i am using repeated subtraction division to handle this, however in compilation the while loop which i use is unable to resolve within 10000 iterations. the loop is shown below:
while (rmdr > "000000000") loop
while (rmdr > "000001001") loop
while (rmdr > "001100011") loop
dig2 := dig2 + '1';
rmdr := rmdr - "001100100";
end loop;
dig1 := dig1 + '1';
rmdr := rmdr - "000001010";
end loop;
dig0 := dig0 + '1';
rmdr := rmdr - "000000001";
end loop;
Any help or insight to this matter would be greatly appreciated.