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Quartus requires loop naming, even if SystemVerilog does not. Is there a way to avoid it? (I could use ModelSim, but I need Quartus for my FPGA.)

Qiu
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marvell
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    Please show us some code where you are trying to omit loop name. Unnamed generate loop can't be used in every situation. – Qiu Jul 19 '15 at 15:28

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Do you mean generate loop labels? Labels for For loops within always/inital blocks are optional.

But generate for loop labels are needed to make the hierarchical paths known in case you want to add constraints, ... Simulators would create a label for unnamed generate loops, something like genblk1, genblk2, ... But synthesis tools need to create hierarchy properly.

I would suggest you add labels for generate if/case/for all the time.

Amal
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