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Im trying to simulate a RAM memory with Quartus and Modelsim by Altera. The problem is that when i assing values to data_inout in the test bench and simulate, the wave is always in 'U' state. It doesnt take any value when i do data_inout <= "0000000000001010"; for example or if i use data_inout <= aux_data; All i want is to test that it write some values on the array and then read them for a college exercise, nothing fancy. Any idea how to simulate it?

Thanks.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram_program is

    port(
        dir : in std_logic_vector (7 downto 0);
        read_write,cs : in std_logic;
        data_inout : inout std_logic_vector (15 downto 0)
        );

end entity ram_program;

architecture code_ram_program of ram_program is 

type tipo_ram is array (255 downto 0) of std_logic_vector (15 downto 0);
signal ram : tipo_ram;

begin
MEM_RAM: process (cs,read_write,datos_in_out,dir)
begin

    if (cs = '1' and read_write = '1') then
        ram(to_integer(unsigned(dir))) <= data_inout;
    end if;

    if (cs = '1' and read_write = '0') then
        data_inout <= ram(to_integer(unsigned(dir)));
    end if;

end process MEM_RAM;

end architecture code_ram_program;
rockstiff
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  • That's right, your simulation is successful! `U` from uninitialised memory and `0` or `1` from your logic resolve to `U`.Now if you made the memory drive `Z` (high impedance) on `data_inout` when you didn't want to read it, you would get a different result. –  Aug 28 '15 at 15:23
  • In addition to driving `data_inout` to all `'Z'`s during write as Brian says there's an error in the sensitivity list of process MEM_RAM. Your example code as shown won't analyze, `datos_in_out` isn't declared (should be `data_inout`). For a behavioral model this isn't particularly accurate. What happens if the address `dir` changes when `cs = '1'` and `read_write = '1'`? –  Aug 28 '15 at 19:29

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