Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of fpga and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also: altera

554 questions

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1 answer

For loop goes into infinite loop when I use a variable as ending condition

I have a for loop that runs fine in Verilog. It looks like this: for(j=0; j<=5; j=j+1)begin ... end but as soon as I change the 5 into a variable: for(j=0; j<=m; j=j+1)begin ... end I get this error: Error (10119): Verilog HDL Loop…

loops for-loop verilog quartus

asked May 09 '16 at 06:31

Jake

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1 answer

VHDL program doesn' t compile

I am trying to create a VHDL ALU with structural way that does the following operations: 1)ADDITION 2)SUBSTRACTION 3)LOGIC AND 4)LOGIC OR I'm running my code in Quartus II and it finds some errors at compilation. Here is my code : library ieee; use…

vhdl quartus

asked May 06 '16 at 13:11

user6230897

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1 answer

VHDL IF Statement in Case Statement

As you can imagine by seeing my code right there, I'm a beginner at VHDL so I'm really wondering why this isn't working as it seems it logically should work. In fact the part that isn't behaving the way that I'd like it to isn't doing anything at…

vhdl fpga intel-fpga case-statement quartus

asked Apr 28 '16 at 09:13

Guillaume Drolet

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2 answers

How to determine if all for loops have ended, VHDL, Quartus-II

I'm struggling with a VHDL conundrum. Here's some code which should explain what I'm trying to do: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.all; entity forLoopTest is -- Number of bits known only at…

for-loop vhdl quartus

asked Apr 19 '16 at 11:24

user3303504

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2 answers

Changing generic value in Quartus doesnt affect the result of compilation

I've got an issue with generics in Quartus. They do work, but if I declare let's say n = 10, and later change it to n = 100, the compilation and simulation results do NOT change. It's as if the generic value was still n = 10. I've tried recompiling…

vhdl fpga quartus

asked Apr 12 '16 at 22:17

Benji

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2 answers

Why is there a difference in output when using Event Control Statement and Delay statement for a simple D Flipflop?

I have created a testbench for a simple positive edge triggered d flip flop with synchronous active-low reset. In the testbench, the first case gives inputs at @(posedge clk), and in the second case, I am giving inputs based on #10ns statements. In…

verilog simulation fpga system-verilog quartus

asked Mar 28 '16 at 08:34

Edwin Joseph

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2 answers

How to instantiate megafunctions in Alteras Quartus-II FPGA IDE

I use the web (ie free) edition of Alteras FPGA IDE. According to the documentation, it hosts at least some of the Altera megafunctions. A response to an earlier tech forum enquiry indicates that it does. I’ve tried to use them, but without…

fpga intel-fpga quartus

asked Mar 22 '16 at 11:46

BruceV

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3 answers

Error : Library "IEEE" does not contain primary unit "numeric_std_unsigned"

I'm using Quartus prime edition v15.1 for writing a register file and I need to use the numeric_std_unsigned package. On compiling, there's an error saying Error (10481): VHDL Use Clause error : design library "IEEE" does not contain primary unit…

vhdl quartus

asked Mar 17 '16 at 19:16

Mohamed Sayed

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1 answer

How can I stop quartus from jumping to the 'compilation report'?

When programming in VHDL I usually compile now and then to validate my code. Quartus makes me jump to the compilation tab every time i press compile, when I just want to check for errors and fix them. This takes up alot of time and I would like to…

quartus

asked Mar 10 '16 at 09:33

sommmen

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1 answer

How to use Quartus to optimize combinational logic?

I am using Quartus to synthesize a combinational circuit to FPGA. Right now I want to get the best possible maximum frequency without considering the resource consumption. The current critical path is composed by a sequence of multiplications like…

fpga multiplication synthesis quartus

asked Mar 07 '16 at 03:34

hooray9

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2 answers

How to create synthesizeable delay?

i got a code like below with clk = #10 ~clk always@ (posedge clk)begin for (g=0;g<8;g=g+1) begin ws = 1; #20 ws = 0; #20; end so is there any other way to make the delay 20 synthesizaeble in the coding above?

verilog quartus

asked Mar 05 '16 at 06:58

Avelyn Goh

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1 answer

How to use float numbers with quartus megawizard ALTMULT_ACCUM(MAC)?

I am using the below mentioned module and testbench to use MAC megawizard in quartus, can anyone tell me how can I use floating point numbers for the same megawizard? Testbench `timescale 1ns/1ps module projecttry2_tb; reg [15:0] A, B; …

verilog quartus

asked Feb 27 '16 at 00:42

Aakash Sarang

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0 answers

quarts II - Qsys PLL error in modsim

Hi I'm trying to use Qsys to create a PLL. The PLL is intended to be used with a serial interface on am FPGA. When I start Modsim to simulate. I get no output from the PLL. Investigating a bit further I tried to load just the PLL in modsim and I get…

vhdl quartus qsys

asked Feb 21 '16 at 22:20

hoboBob

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1 answer

VHDL sequential conditional signal assignment statement error

In my VHDL code I have an error in sig_out_real <= X"00" & sig_in when sig_in(7)='0' else X"ff" & sig_in;. I don't think it is a syntax error. But Quartus shows an error at that point. I don`t understand why it's an error. Can anyone provide…

vhdl quartus

asked Feb 14 '16 at 05:17

Kim

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1 answer

Verilog Ports in Generate Loop

For reasons which cannot be avoided (requirements of Qsys), I have several Verilog modules which end up with many ports which would be far easier to work with if they were packed. To try and explain what I mean, here is an example: module foo #( …

verilog quartus qsys

asked Feb 14 '16 at 02:41

Tom Carpenter

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