How to use/declare an unsigned Integer value in VHDL?

Question

I'm trying to design a basic Vending machine on a Altera DE1-SoC Board. My question comes from trying to code the State Machine that will control the vending process. How do you track the $ value being added jumping between states? I think the code I'm trying to implement is written in a higher level language format and is not being able to be compiled in VHDL. Any ideas?

I'm getting this error (right after the Architecture declaration):

Error (10482): VHDL error at State.vhd(21): object "unsignedInteger" is used but not declared

library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_unsigned.all;

    entity MessageState is
    Port(
        Reset          :in   std_logic; -- reset to a safe state
        -----------------------------------------------------------------------------------
        MyStateOut  :out    std_logic_vector( 1 downto 0 ); -- drive the current state to display or LEDs 
        OutputCode  :out    std_logic_vector( 6 downto 0 ) -- to the display driver 
    );

    end;

    architecture Vending_FSM of MessageState is

    signal Count: unsignedInteger(8 downto 0);

    -- we define a data type to represent the states. Use descriptive names
    -- add more lines for more states. Change the size of MyState as needed
    subtype MyState is std_logic_vector(2 downto 0);

    constant Idle          :MyState := "000";
    constant NickelState  :MyState := "001";
    constant DimeState    :MyState := "010";
    constant QuarterState :MyState := "011";
    constant Dispense       :MyState := "100";

    signal state, next_state: MyState;

    begin

    MyStateOut <= state; -- make state visible.

    MyNextState: process(state, next_state) begin -- add all signals read or tested in this process

        case state is

        when Idle =>

            if ( KEY(0) = '1') then
                next_state <= NickelState;

            elsif ( KEY(1) = '1') then
                next_state <= DimeState;

            elsif ( KEY(2) = '1') then
                next_state <= QuarterState;

            else
                next_state <= Idle; -- default action
                Count <= (others => '0');

            end if;

score 2 · Accepted Answer · answered Nov 05 '15 at 21:50

2

1) Remove use IEEE.std_logic_unsigned.all; because numeric_std is already loaded. It declares the SIGNED and UNSIGNED data types.

2) The type for your signal Count is just UNSIGNED.

answered Nov 05 '15 at 21:50

Paebbels

15,573
13
70
139

That fixes it, thanks! Is this a good way of approaching this task? Or is there a more optimal way? – VKkaps Nov 05 '15 at 21:55
1

a) You could use an enum for your state instead of many constants. b) Signal state has no default value. c) Your process/FSM has no default assignments for FSM outputs -> this could leed to latches. – Paebbels Nov 05 '15 at 22:01

How to use/declare an unsigned Integer value in VHDL?

1 Answers1