Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

Xilinx, Inc.
Altera Corp. (now Intel FPGA)
Atmel Corp. (now Microchip Technology Inc.)
Lattice Semiconductor Corp.

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions

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1 answer

How can I connect multiple FPGA and send large data back and forth?

Let's say I have 4 identical FPGA boards running. They are doing some neural network calculation. All of them need to send/ receive data from each other back and forth and do their own calculations using that data. What is the best way/ IP/ protocol…

fpga

asked May 24 '22 at 19:29

nadiatimuj

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1 answer

Type of identifier does not agree with its usage as "boolean" type - VHDL in Quartus

I'm developing a simple buffering system in VHDL. I get the error I mentioned in the title for "empty" whenever I try to compile. I don't know why it won't let me invert a std_logic type. I've also been getting errors about the comparisons. For some…

vhdl fpga identifier hdl quartus

asked May 24 '22 at 13:43

Aryan Prasad

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1 answer

Weird behavior of dpc++ code after running it on FPGA device

I am using DPC++ to accelerate knn algorithm on FPGA device. The following code is the code I wrote for the euclidean distance. The problem is that the fpga_emulation works very well with no problems while running it on fpga hardware (Intel Arria 10…

intel fpga parallel.for sycl dpc++

asked May 19 '22 at 18:53

Amal Taha

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1 answer

FIR lowpass filter module error during simulation

This is an FIR lowpass filter module that uses a Kogge Stone Adder for addition. The error seems to occurs when the Kogge stone adder circuit is used. the module works fine if the kogge stone adder part is removed (line 38 -72) and if line…

verilog fpga xilinx hdl vivado

asked May 19 '22 at 06:44

jomon

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1 answer

Generating number sequence in verilog (automat)

I was given a task to create verilog code that generates number sequence 323135343355. It should be generated like automat so it has states and next number in sequence is generated according to its previous output. Task should be done in two…

verilog fpga number-sequence

asked May 13 '22 at 10:36

SKImperator

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1 answer

VHDL Frequency Meter that reads NCO

vhdl frequency fpga quartus nco

asked May 08 '22 at 19:07

Pouyaiiv

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1 answer

understand Finite state machine in a verilog

I am using an Artix 7 FPGA and writing my code in Xilinx ISE. I already have the Verilog code for the project I am working on. Unfortunately, I am not able to understand this module- The full code is posted here. My goal is to find out where these 6…

fpga fsm

asked May 03 '22 at 20:43

adfty

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1 answer

Dual clock FIFO in vivado (verilog)

I want to use a FIFO in a project where a state machine buffers as much data as possible to a FIFO, which will then be processed by a DSP block. To maximize data throughput I want to use multiple QSPI nor flash modules as a ROM with a wide data bus.…

fpga fifo vivado

asked Apr 30 '22 at 10:49

OM222O

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2 answers

How to check the state machine case in testbench

I am writing a code for spi slave and wishbone bus. The issue is that the testbench file shows all the signals correctly (the signals and ports that are used in testbench) but when I am trying to check the state machine in the main code it shows…

vhdl fpga

asked Apr 27 '22 at 08:14

Taha Alars

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2 answers

Lowering the clock frequency for my circuit in Vivado

I have a circuit like this module control(input clk, output out); reg [63:0] r0 = 1, r1 = 2, r2 = 3, r3 = 4, r4 = 5; always @ (posedge clk) begin // some logic with a high delay -- representative of my actual project r0 <= (r0 +…

fpga clock vivado

asked Apr 20 '22 at 22:02

mimo31

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1 answer

VHDL - Using output of one entitiy as input of another

I am trying to make a basic distance indicating module using ultrasonic sensor. When I dumped the code for the same into my FPGA board(Helium V1.1 developed by IIT-B) all the LEDs in the board started glowing since the clock frequency was too high.…

vhdl fpga quartus

asked Apr 16 '22 at 11:52

Bojack Horseman

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0 answers

How to use the audio output in a DE10 Standard board using c?

I just want to play a simple tone when a variable is set to true, I can't find any examples of this using c. Any help would be greatly appreciated. I know its broad but thats because any way of doing it using c should be fine. Board Manual:…

c fpga

asked Apr 12 '22 at 15:46

Logoapp

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1 answer

For loops for reading data from a ROM Block in Verilog

I asked this question yesterday, but it was closed because I was unable to provide code for the problem and relevant waveforms. Hence, this is an updated version of the question yesterday. I am trying to write to an array of registers using for…

arrays verilog fpga vivado

asked Apr 11 '22 at 13:25

Jiren

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1 answer

modelsim simulation time cycles appear to be different than test_bench

i have a testbench which states at the top: 'timescale 1 ns/ 1 ps a clock which is defined as: code in testbench always begin #5 sys_clk = ~sys_clk; #20 clk_in = ~clk_in; #8 clk_acq = ~clk_asq; end run the simulation using a do file: vsim…

verilog simulation fpga hdl modelsim

asked Apr 05 '22 at 11:34

Dan

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1 answer

Machine state does not change output

As you can see in the code below, I have a machine state with a state called start. This state should take the value of coord_x_reg , increment it by one and assign it to the output port using the assign instruction at the end. The problems…

verilog fpga xilinx xilinx-ise

asked Apr 01 '22 at 20:48

Ginés Díaz

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