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I want to use a FIFO in a project where a state machine buffers as much data as possible to a FIFO, which will then be processed by a DSP block. To maximize data throughput I want to use multiple QSPI nor flash modules as a ROM with a wide data bus. DSP blocks can perform 1 operation per cycle which means the data input width has to be larger than the output width (because it takes 8 clock cycles to transfer data). For example, I want a FIFO with 32-bit input and 8-bit output, but this is not supported in vivado as far as I can tell. I tried the various FIFO block generators and even tried using the macros but I'm not having much luck.

Please let me know how I can generate a dual clock FIFO with a larger input width than the output width.

toolic
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OM222O
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Using FIFO Generator IP core in Vivado, choose Independent Clocks Block RAM for FIFO Implementation and then you will be able to set larger data width for write port than the read port.

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mohammadhgh
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  • that is exactly the opposite of what I want to do. I want a wider read port. Again let's assume it takes 8 cycles to load 1 byte and the DSP can process 1 byte per clock cycle. That means there are 7 wasted cycles, but if we load 8 bytes using a larger read port, there are no wasted cycles, and data is processed as a continuous stream. – OM222O Apr 30 '22 at 16:58
  • @OM222O You said " I want a FIFO with 32-bit input and 8-bit output". FIFO inputs are write port and FIFO outputs are read port. So your question should be a FIFO with larger input port than output port which is still possible with the same method. – mohammadhgh May 07 '22 at 08:34
  • you're right, sorry about that! I was reading that at 2 AM and my brain wasn't working! – OM222O May 07 '22 at 17:36