Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

Xilinx, Inc.
Altera Corp. (now Intel FPGA)
Atmel Corp. (now Microchip Technology Inc.)
Lattice Semiconductor Corp.

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions

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1 answer

Diamond/ModelSim post-route timing simulation problems

I’m new to TinyFPGA, so I need a little help! I’m working on a Tiny FPGA project for sensors and actuators where each tinyFPGA provides an 8 bit digital sensor input, and a 4 actuators output with different modes of operation (on/off, PWM, and…

fpga modelsim lattice-diamond

asked Oct 02 '21 at 11:17

Jonas

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1 answer

How can you control Kristen FPGA from implementing excess registers?

I am using Kristen to generate a Verilog FPGA host interface for a neuromorphic processor. I have implemented the basic host as follows,

fpga

asked Sep 24 '21 at 19:18

Nolen White

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0 answers

Why is indexing necessary on histograms?

I'm currently reading the book Design for Embended Image on FPGAs chapter 7 about histograms, and my big question is why during the construction of the histogram is necessary to index the output of the counters? Here's a image of this photo Thank…

image image-processing histogram fpga

asked Sep 21 '21 at 03:11

MeowYOU

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1 answer

VHDL Modelsim: Array lengths do not match (null array vs array of length 8)

I was wondering why I am some of my std_logic_vectors are showing up as null vectors especially when I specified the length already. I'd appreciate any help possible library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity…

arrays vhdl fpga modelsim

asked Sep 13 '21 at 05:01

Bruce Huynh

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2 answers

Why is my counter out value producing StX?

I made a simple counter that goes to 32 and a testbench for it. I'm not sure why the value for the output (co) is still coming out as StX. I've been trying to debug this for many hours now and I'm not sure of the issue.

verilog fpga test-bench

asked Sep 03 '21 at 15:18

Bruce Huynh

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1 answer

aocl command not working correctly when run from github actions

I'm trying to get github actions to work with Intel FPGAs in a self hosted runner. Any time communication from the host to the FGPA is attempted there are errors like these ones: Error initializing DMA: invalid parameter Error initializing DMA:…

github opencl github-actions fpga intel-fpga

asked Sep 01 '21 at 21:45

tgonzalez89

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1 answer

How parallel are FPGAs?

i come for GPU world. When i submit to the GPU an image 1024x1024 pixels to be processed, i know that there are not 1048576 threads running in parallel on the GPU. If the wavesize of the GPU is 64, then 64 threads truly run in parallel for real. And…

parallel-processing fpga

asked Aug 26 '21 at 02:49

Pipi

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0 answers

Viewing Microblaze Processor Output with out Serial Port

I am experimenting with some Old Legacy Spartan 3 , 6 and Virtex 5 Series Kits as a part of research work. I am currently designing a microblaze processor systems. Is it possible that without using RS232 cable interface I can view the results on…

fpga xilinx spartan microblaze xilinx-edk

asked Aug 22 '21 at 07:57

Arslan Majid

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1 answer

VHDL - Why is it bad practice to not include an else-condition in a "process" block?

I'm watching a beginner tutorial on VHDL. The lecturer says that it's bad practice to not include an else-condition inside a "process" block because it will create a latch and is bad for timing in advance circuits. He said that including an…

vhdl fpga

asked Aug 12 '21 at 14:28

GrandNecro

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0 answers

Replace pointer to pointer LLVM

I am trying to make a front-end output providing LLVM IR compatible with LLVM IR for FPGAs (backend goal). So the problem is that FPGAs can't handle pointer to pointers due to memory allocation issues. However, my front end provides me with a…

pointers llvm fpga llvm-ir

asked Aug 04 '21 at 11:10

RicDen

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1 answer

How to Write data from FPGA to DDR3 memory without PS Logic

I'm using zynq7000 family fpga, i want to write data from my fpga to micron ddr3 sdram memory without using PS logic (only using PL) I'm new to memory based designs may i get any help to design the logic using PL or any references. Thanks in…

fpga xilinx xilinx-ise register-transfer-level

asked Jul 14 '21 at 12:08

manu

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1 answer

how to use Xilinx FPGA RAM?

For example entity xilinx_TDP_RAM is generic( ADDR_WIDTH : integer := 32; DATA_WIDTH : integer := 129; ENTRIES : integer := 32 -- number of entries (should be a power of 2) ); port( clk : in std_logic; -- clock …

fpga ram

asked Jul 11 '21 at 13:41

newer

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1 answer

Controlling ADC data rates using FPGA

I need to control sampling frequency of ADCs interfaced with my FPGA. I can use a 50MSPS, 14 bit resolution ADC. and then using DCM divide the FPGA source 50MHz clock to 1MHz, 2MHz and 5MHz and use these frequencies each time as the clock of my…

vhdl fpga xilinx adc xilinx-ise

asked Jun 14 '21 at 12:51

Fateme

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1 answer

Communication between FPGA and Aria V HPS?

I want to make communication using Altera MM Mailbox IP component, between Aria V hps and my nios processors. Project in Qsys I managed to write down C code for Nios processors (FPGA side) to work with mailbox IP, then I made header file for HPS…

c fpga intel-fpga nios qsys

asked May 23 '21 at 10:45

techno

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1 answer

Error: "Failed to find 'return' in hierarchical name 'return" when simulate in ModelSim

i'm writing a verilog program. When i compile, there is no error. But when i simulate this program, there is an error: "MixColumns.v(14): (vopt-7063) Failed to find 'return' in hierarchical name 'return'." What should i do to fix this problem ?…

verilog fpga modelsim

asked May 21 '21 at 03:38

nghihoang2207

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