modelsim simulation time cycles appear to be different than test_bench

Question

i have a testbench which states at the top:

'timescale 1 ns/ 1 ps

a clock which is defined as:

code in testbench

always begin
   #5 sys_clk = ~sys_clk;
   #20 clk_in = ~clk_in;
   #8 clk_acq = ~clk_asq;
end

run the simulation using a do file: vsim in do file

but the clock period in ModelSim waveform, when measured by the cursor, is:66ns and not 10ns clock waveform any idea?

I don't really understand what causes this behavior.

Edit: also, if i run the fallowing commands in the TESTBENCH:

initial 
begin
#1 $display("T=0t at time #1",$realtime);
#1 $display("T=0t at time #2",$realtime);
#1 $display("T=0t at time #3",$realtime);
#1 $display("T=0t at time #4",$realtime);
#2 $display("T=0t at time #5",$realtime);
end

i get:

T=1000 at time #1
T=2000 at time #2
T=3000 at time #3
T=4000 at time #4
T=6000 at time #5

I guess this is a clue, but i have no idea what causing it.

score 0 · Accepted Answer · answered Apr 05 '22 at 13:48

0

You should have put all the code in text form. You generate clocks following this scheme:

always begin
   #5 sys_clk = ~sys_clk;
   #20 clk_in = ~clk_in;
   #8 clk_acq = ~clk_asq;
end

So, your clocks are updated every 33 cycles: 5 + 20 + 8, which explains clock period of 66.

An always block does not run parallel jobs, nor it restarts till it finishes. So, it will go through all updates before it starts again. As a result all your clocks will have a period of 66 and just will have an offset relative to each other.

answered Apr 05 '22 at 13:48

Serge

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Huge face palm! @Serge great answer, thanks!!!!. So coming in from VHDL, when i had multiple clocks i wanted to simulate, i would have done something similar, only with `code` "clk<= not clk after 5 ns; `code` Verilog: is there a similar solution? or shoud i do a separeate always clock for each clock? also, what about the clock ticks? why is it jumping as 1000,2000,3000 – Dan Apr 06 '22 at 04:39
just split the lines into different *always* blocks and the clocks will run in parallel. Do **not** use <= with clocksl – Serge Apr 06 '22 at 13:33
Yeah that is what i did,. I understand why using "=" was a mistake, using a sequential operator, was a mistake as you pointed out, but why "<=" a non-blocking operation does not work either, why is that a mistake, as you said, when trying to drive several *parallel* clock signals. seems to me like a non clocking assinment is exacly what i am looking for. – Dan Apr 07 '22 at 04:24
`=` is correct: `always #5 sys_clk = ~sys_clk; always #20 clk_in = ~clk_in; ...`. If you use `<=` there instead of `=` you cause race condition in sequential logic later on. – Serge Apr 07 '22 at 10:33

modelsim simulation time cycles appear to be different than test_bench

1 Answers1