Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

Xilinx, Inc.
Altera Corp. (now Intel FPGA)
Atmel Corp. (now Microchip Technology Inc.)
Lattice Semiconductor Corp.

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions

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Wait until =1 never true in VHDL simulation

Below is the code that I am running. My question is why doesn't the 3rd wait until trigger in modelsim? The console output is simply GOT HERE. It never gets to the line GOT HERE 2. I would think that having the same wait until = 1 twice…

vhdl fpga modelsim

asked Dec 09 '13 at 22:02

Russell

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is there a verilog tutorial where you build a very simple microprocessor?

I'm a programmer wishing to learn verilog. What would be amazingly neat would be a tutorial where one constructs a tiny microprocessor with a very clean design, something like an Intel 4004, and then goes on to actually make it using an fpga and…

verilog fpga microprocessors

asked Apr 25 '12 at 19:18

John Lawrence Aspden

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6 answers

Random number generation on Spartan-3E

I need to generate pseudo-random numbers for my genetic algorithm on a Spartan-3E FPGA and i want to implement it in verilog: could you give me any pointers on this?

hardware random verilog fpga

asked Apr 16 '09 at 17:15

akosch

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4 answers

Implementing a real-time, run-time compiler on an FPGA

I'm curious to hear people's opinions on how hard it would be to implement a compiler on an FPGA. This could just be a compiler backend, LLVM for example, and the implementation would just take in LLVM IR and output machine code. The purpose of this…

compiler-construction real-time llvm fpga

asked Jun 05 '11 at 20:56

runeks

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Approximate e^x

I'd like to approximate the ex function. Is it possible to do so using multiple splines type based approach? i.e between x1 and x2, then y1 = a1x + b1, between x2 and x3, then y2 = a2x + b2 etc This is for dedicated fpga hardware and not a…

math optimization fpga

asked Aug 08 '11 at 15:22

trican

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2 answers

Testing FPGA Designs at Different Levels

Various aspects of test strategies for FPGAs have been discussed here on SO but I can't find that the following question has been asked/discussed/answered: At what levels should you simulate your FPGA design and what do you verify at each level? If…

testing vhdl verilog fpga

asked Sep 03 '15 at 17:05

lasplund

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3 answers

Compile Date and Time in FPGA

Can I uses in VHDL something similar to the C-Sourcecode-Macros __DATE__ and __TIME__ to make the compile time available in the FPGA as a kind of version time stamp? As a >>>new-comer<<< to VHDL I want to modify the following existing code, which…

vhdl fpga intel-fpga nios

asked Aug 09 '13 at 07:19

Helmholtz42

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3 answers

How to program FPGA using F#

I usually use F# for writing numerical algorithms. Functional programming constructs in F# helps to express algorithms in a very natural way. I often end up with a succinct and understandable implementation, and may be able to parallelize it quite…

f# parallel-processing fpga

asked Dec 05 '11 at 22:11

pad

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How to initialize contents of inferred Block RAM (BRAM) in Verilog

I am having trouble initializing the contents of an inferred ram in Verilog. The code for the ram is as below: module ram( input clock, // System clock input we, // When high RAM sets data in input lines to given address …

verilog fpga xilinx vivado

asked Apr 13 '16 at 22:15

Paulo C

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2 answers

What is the practical difference between implementing FOR-LOOP and FOR-GENERATE? When is it better to use one over the other?

Let's suppose I have to test different bits on an std_logic_vector. would it be better to implement one single process, that for-loops for each bit or to instantiate 'n' processes using for-generate on which each process tests one…

for-loop vhdl fpga hardware asic

asked Jul 13 '15 at 21:16

Felipe GM

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2 answers

Time stamp in VHDL

is there any function in VHDL which is used to get current simulation time at which a process is running? May be same like the function in systemC sc_time_stamp()

vhdl fpga

asked Dec 03 '13 at 15:24

Digeek

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2 answers

Triggering signal on both edges of the clock

Design requires a signal to be activated at specific circumstance on rising edge of the clock, and deactivated at another circumstance on falling edge of clock. Here's what I think: always@(posedge CLK) begin signal1 <= 1'b0; // reset flag …

verilog clock fpga

asked Oct 26 '13 at 10:59

Anonymous

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4 answers

VHDL: creating a very slow clock pulse based on a very fast clock

(I'd post this in EE but it seems there are far more VHDL questions here...) Background: I'm using the Xilinx Spartan-6LX9 FPGA with the Xilinx ISE 14.4 (webpack). I stumbled upon the dreaded "PhysDesignRules:372 - Gated clock" warning today, and I…

vhdl clock fpga

asked Mar 06 '13 at 10:37

MartyMacGyver

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How to launch Xilinx ISE Web Pack under Ubuntu?

I've downloaded and successfully installed Xilinx ISE Web Pack 14.4 on Ubuntu 12.10 although I'm unable to launch it.

fpga xilinx

asked Feb 27 '13 at 18:40

Can

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Fast, small area and low latency partial sorting algorithm

I'm looking for a fast way to do a partial sort of 81 numbers - Ideally I'm looking to extract the lowest 16 values (its not necessary for the 16 to be in the absolutely correct order). The target for this is dedicated hardware in an FPGA - so this…

algorithm sorting vhdl verilog fpga

asked Nov 09 '12 at 10:28

trican

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