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Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

When asking a question, specify a manufacturer and FPGA model family if applicable.

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OpenCL FPGA: Kernel Execution of 2 copies of same kernel is not being made in parallel. In addition to that, there is also idle time in between them

My goal is to complete FFTs of 2 - 4K Data points together. Hence, I made 2 kernel objects from the same kernel and Enqueued the tasks at once, i.e. without any Buffer Read-Write or any callbacks in between. I find out that it doesn't happen that…
Raghuttam Hombal
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difference between "Coverage summary by istance" and "Design Unit Coverage Details"

In an FPGA project what is the difference between: Coverage summary by istance Local Istance Coverage Details Recursive Hierarchical Coverage Details Design Unit Coverage Details
KemKing
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Getting nan values from OpenCL FFT kernel on FPGA

I was trying to use the Intel's FFT1D kernel by writing the Host program by my own for Intel FPGA. Link to Intel's FFT1d can be found here I have also given my host program below, wherein, I have a file saved (which contains some data), my task is…
Raghuttam Hombal
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Is there an open source H.264 implementation on FPGA?

I want to design and implement an H.264 baseline/main profile encoder on FPGA for real-time HD video processing. To begin with, I am looking for design examples that would help me to understand the H.26 implementation on FPGA. Therefore, is there…
cuteolaf
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vivado HLS or SDsoc for use openCV

I want to do an image processing by openCV on FPGA . But I do not know if I should use the SDsoc method or the vivadoHLS method. The size of the images I am going to process is large and I want to solve the problem through parallel processing. What…
tom
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Partitioning combination and sequential logic for reliable and low latency butterfly module for a 4 stage FFT design

I am building a 4 stage FFT using a simple butterfly module to do the complex multiply and accumulate. I have build the simply butterfly module (see below). I need some input on having the minimal latency and at the same time have a stable…
user2532296
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Different resource utilization shows in vivado hls and vivado

I implemented this loop calculation in vivado HLS. For (i = 0; i < 59; i++){ #pragma HLS unroll tmp = C[i]; For (j = 0; j < 3; j++){ #pragma HLS unroll tmp = tmp + A[j][i] * B[j]; } C[i] = tmp; } The DSP48E utilization…
hdcoe
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VHDL - Upper digit output does not go up from '0000', when implementing two-digit-bcd-counter

I'm trying to implement two-digit-bcd-counter in VHDL, by referring to this diagram: This is my code for it: library ieee; use ieee.std_logic_1164.all; entity two_digit_bcd_counter is port( v_cc : in std_logic; clk : in std_logic; …
theCursedPirate
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Eth could work with Kintex US without DDR option enable?

I have a custom board which i'm trying to test a ping test using Eth from Microblaze master with no DDR Support. Technically , to check if this option is actually exists , i took an EVB - KCU105. And as part of my testing, i have used a stable…
Amir Timsit
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Output not as expected when implementing 4-bit SISO register in VHDL

I am trying to create a 4-bit SISO register in VHDL, and this is my main code: library ieee; use ieee.std_logic_1164.all; entity right_shift_siso_reg_4 is port( D_in : in std_logic; clk : in std_logic; D_out : out std_logic ); end…
theCursedPirate
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Provide input data to FPGA using USB

I am working on Xilinx Spartan 3E platform, using this development board: http://www.xilinx.com/products/boards-and-kits/HW-SPAR3E-SK-US-G.htm My program operates on certain data and then provides output. I wish to transfer the input signals…
Neel Mehta
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Simulation Waveform in Intel Questas_fse/Quartus II doesn't update outputs

I'm attempting to run Quartus II ( Quartus Prime Version 21.1.0 Build 842 10/21/2021 Sj Lite Edition) on linux Pop OS 21.10. I fail to produce result on output from Questas simulation run from the Simulation Waveform Editor. Project Settings I have…
NRagot
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iceprog - Can't find iCE FTDI USB device with Alchitry CU

I'm trying to upload my build code to my alchitry-CU FPGA board threw apio using iceprog on windows. apio upload which then executes iceprog -d i:0x0403:0x6010:0 hardware.bin And the output is init.. Can't find iCE FTDI USB device (device string…
Lopfi
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How to use only one DUT for different test cases in a VHDL testbench and how to detect SPI master's mode on the slave side?

First I would like to mention that I'm still new to the VHDL World so please bear with me. Currently, I'm working on an SPI project where I created a generic master module that can send and receive different data widths ranging from 8 to 64 bits.…
Amr
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How to use only one ADC channel on MAX10

I have an ADC core component adc_qsys is port ( adc_1_command_valid : in std_logic := '0'; adc_1_command_channel : in std_logic_vector(4 downto 0) := (others => '0'); …
john7
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