Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

Xilinx, Inc.
Altera Corp. (now Intel FPGA)
Atmel Corp. (now Microchip Technology Inc.)
Lattice Semiconductor Corp.

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions

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2 answers

Finding Absolute Value In Verilog Data Designated by System C/Xilinx X

I have been trying to find the Absolute value of an integer which is designated to Verilog core using Xilinx SystemC, what I have seen is that Verilog treats the negative number as a positive number. I have tried all data types : signed int , int,…

asked Aug 11 '11 at 10:13

aibk01

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1 answer

Why does Xilinx's Multiplier IP product bitwidth have an extra bit?

Xilinx's complex multiplier IP documentation (PG104) has this to say about input and output bit-width setting: Output Width: Selects the width of the output product real and imaginary components. The values are automatically initialized to provide…

binary vhdl fpga xilinx

asked Dec 02 '21 at 18:38

aquaticapetheory

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1 answer

Cant instantiate a softprocessor design in quartus because of compile errors(Error10170)

I've made a design in platform design in quartus ver 18.0 and I want to instantiate it in a template design I made for the MAX10DE10 lite development kit I try to compile it and it gives me this error: Error (10170): Verilog HDL syntax error at…

fpga quartus

asked Nov 29 '21 at 17:47

guigenta

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1 answer

Make a delay after falling edge of signal and then do something in VHDL

I would like to know how I can do the following operations in this order: First detect the falling edge of an input signal (rd), then wait for 15 ns and finally make the necessary changes in the variables, for example store the db_input 8bits vector…

vhdl fpga intel-fpga

asked Nov 21 '21 at 11:26

Alejandro Fernández Suárez

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2 answers

Cascading BRAM in iCE40 FPGA

I'm really new to FPGA and Verilog. I've been working on the Tri-SPI PHY controlling Noritake Itron VFD Display. One of the feature I want to implement is the framebuffer memory on the FPGA itself. I'm using the iCE40LP1K which has 64kbit BRAM…

verilog fpga lattice hdl ice40

asked Nov 16 '21 at 12:51

TinLethax

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1 answer

Is it possible to configure the same tdata width on the masters and slaves interfaces on the axi4-stream switch IP of xilinx?

I have to connect an AXI-stream switch IP into my FPGA VIVADO design, the switch have two slaves and one master. The data width inbound is 32 bits and I need data width outbound to be as well, but no matter how I configure the IP, it seems that the…

ip bit fpga xilinx vivado

asked Nov 16 '21 at 10:28

rony sitbon

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0 answers

USB Errno 5 when uploading to a TinyFPGA BX with tinyprog

I have a TinyFPGA BX board that is connected to a Mac (Big Sur) I am trying to upload a new bootloader to this board using tinyprog (https://pypi.org/project/tinyprog/). I am running this with >>>from tinyprog import * >>>from tinyprog.__main__…

python fpga ice40

asked Nov 14 '21 at 16:33

wombatbutt

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1 answer

How to boot ddr memory of an FPGA?

I have nexys 4 ddr board which has 128MiB on board memory and I access it via IP inside Vivado named Memory Interface Generator. But for example unlike BRAM IP which has a .coe file that initialize BRAMs of the board, here for ddr memory of the…

fpga riscv vivado

asked Nov 14 '21 at 10:32

Seyed Kian

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1 answer

Generating multiple delayed channels in FPGA

Trying to find a way of implementing on an FPGA a multi channel delayed signal in real time. My intention is to A/D a continuous audio signal and split the signal into 10 output channels with each channel time delayed by differing delay amounts. The…

fpga

asked Nov 10 '21 at 02:33

Vox

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1 answer

Add two numbers using nioss2 processor in FPGA

I'm new to FPGA and nios2. I want to add two integers using niosII. When I going to add two integers I wrote a C code like this. #include "stdio.h" #include "io.h" #include "system.h" int main() { unsigned int a = 24,b=56,c,ans; c=a+b; …

c fpga nios

asked Nov 01 '21 at 09:39

Maya Innovatios

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0 answers

How do you take an output from a clock counter in verilog?

I am trying to make an led on the DE0 FPGA turn on every 8 button presses. I have written the code for a counter, but the led is turning on every other button press, not every 8. Here is what I have: module tima(output led, input reset, input…

verilog fpga

asked Oct 28 '21 at 20:19

josed2212

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1 answer

HLS: How to separate AXI4 signals

I am trying to write a module that uses the AXI4 streaming protocol to communicate with the previous and next modules. The modules use the following communication signals: TDATA, which is 16 bits, TKEEP, which is 2 bits, TUSER, which is 1…

fpga xilinx vivado vivado-hls

asked Oct 22 '21 at 10:42

Skilopsaros

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1 answer

Make a 4-bit adder fit in a single slice using Xilinx 7 series and CARRY4 in verilog

I am trying to make a 4-bit adder using the CARRY4 primitive in the 7 series using verilog. The module I wrote was the following: module fast_4adder( input wire [3:0] a, input wire [3:0] b, input wire c_in, input wire…

verilog fpga xilinx

asked Oct 15 '21 at 22:11

Arne Cl

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1 answer

applying stimulus to FPGA using PC

Is there any way I can apply stimulus signals on my FPGA board from my PC itself, and view the output of hardware in any simulation software? I am working on Spartan 3A development board provided by numato labs (elbert…

fpga vlsi digital-design

asked Oct 14 '21 at 10:45

Sparsh

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0 answers

Synthesis getting stuck and not finishing due to this block of verilog code... any ideas why?

This is the block of code causing the synthesis to get stuck always @ (posedge M_AXIS_ACLK) begin if(force_enable && !stop_signal) begin for (j=0; j <31; j = j+2)begin buffer_data[j+buffer_counter] <=…

verilog fpga vivado

asked Oct 02 '21 at 21:17

Hussam Abedlatif

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