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I am using an Artix 7 FPGA and writing my code in Xilinx ISE.

I already have the Verilog code for the project I am working on. Unfortunately, I am not able to understand this module- The full code is posted here.

My goal is to find out where these 6 states are defined in the FSM: Reset (000), Wait for password (010), Compare (100), Log in successful (110), Login failed (111), and Do operation (101) and change the encoding to 4 bits.

I don't understand how the FSM in the image is there in the code.

Is anyone generous enough to help, please? Can I get a description of what is being done here?

toolic
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adfty
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1 Answers1

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The posted code is not Verilog RTL (Register Transfer Level) source code. Rather, its a post synthesis Verilog netlist. It contains the vendors primitives, look up tables (LUTS, buffers, etc). There is no way to understand the correlation between the bubble diagram and a post synthesis netlist in code linked to, its machine generated by the FPGA build tool (ISE in this case).

To correlate the bubble diagram and code, locate the corresponding Verilog source code that was used to create the netlist.

You might be able to locate the source code like this: If you are on Linux, cd to near where the code is located and run

find . -iname '*.*v' | xargs grep 'Compare'

Here is an example of what a Verilog RTL state machine would look like:
https://www.asic-world.com/tidbits/verilog_fsm.html
The state variables and related logic are represented as parameter names (Verilog) or enumerations (in SystemVerilog). The state names are searchable using a text editor.

Mikef
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  • May I ask if it means that somebody wrote the Verilog RTL first and then translated it to the post-synthesis netlist? All other modules are however written in Verilog RTL so I was wondering why this would be the case? – adfty May 03 '22 at 23:01
  • Thanks. Also what's 'iname' in the linux command? I put in this command in the code directory but nothing happens. – adfty May 03 '22 at 23:04
  • To your first comment question: Synthesis is part of the build workflow which creates a .bit file to be downloaded into your FPGA. Here is a reference: https://hardwarebee.com/ultimate-guide-fpga-design-flow/ – Mikef May 03 '22 at 23:20
  • To you 2nd comment question: -iname is an argument to the Linux command find. Here is a reference for the Linux find command. https://www.computerhope.com/unix/ufind.htm – Mikef May 03 '22 at 23:22
  • Thank you. I know what synthesis is. I also know how verilog RTL FSM looks like, I just couldn't understand that this one module in the design is post-synthesis netlist verilog. Is there any way to get the verilog RTL from this netlist other than manually? I am not getting anything when I put in the command that you showed in the answer. Also, why would someone want to have a post-synthesis netlist verilog in one module and verilog RTL in the rest? This doesn't make sense to me. Sorry for asking too many questions. – adfty May 03 '22 at 23:31
  • To your 4th comment question: There is no way to get RTL from a post synthesis netlist. – Mikef May 03 '22 at 23:58
  • To our 5th comment question: If find does not run at a Linux prompt talk to your Linux admin there is a problem with your system. – Mikef May 03 '22 at 23:59
  • To you 6th comment question: For my projects I write RTL and store in a separate directory structure than the netlist. The tool settings determine what folder the netlist ends up in. – Mikef May 04 '22 at 00:01
  • If you found this helpful, please accept the answer and upvote the question. – Mikef May 04 '22 at 00:02
  • The question was **why** would someone want to have a post-synthesis netlist verilog in one module and verilog RTL in the rest? Not how. – adfty May 04 '22 at 09:12
  • The point is - I was given this code to work with and except for 1 module, all modules of the design are in Verilog RTL, hence I was wondering about the motivation for this. – adfty May 04 '22 at 09:13
  • It a good question, I would ask the person or group that delivered you the code. – Mikef May 04 '22 at 13:04