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I am writing a code for spi slave and wishbone bus. The issue is that the testbench file shows all the signals correctly (the signals and ports that are used in testbench) but when I am trying to check the state machine in the main code it shows nothing red line. I tried to define an output port and assign the state to it, it did not work because I don't know how to make an output port as a string because the state is like this

TYPE wb_state_t IS
  (
    WB_IDLE,
    WB_WRITE,
    WB_READ,
    WB_FINISH
  );

SIGNAL   wb_state : wb_state_t;

I want to assign wb_state to an output port so I can check the state in the testbench. How can I do that?

Masoud Keshavarz
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Taha Alars
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  • To create a port of the state type, you will need to define the state type in a package so that it is visible in the entity declaration region and any other files that need to have the type visible. – Tricky Apr 27 '22 at 08:19
  • @Tricky yes, now it makes sense. Do you have an example of how can I build a package for state machine cases? thank in advance – Taha Alars Apr 27 '22 at 08:29
  • Simply create a package, like any package, with your state machine type cut and pasted into it. – Tricky Apr 27 '22 at 08:38

2 Answers2

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As you read in the comments, I only needed to make a simple package and put the state machine cases in it and call it in both the top level and the testbench files.

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
    package wb_state_machine is 
             TYPE wb_state_t IS
      (
        WB_IDLE,
        WB_WRITE,
        WB_READ,
        WB_FINISH
      );
      end package;
Taha Alars
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lot of simulator are able to display internal signal. for instance on vivado or Questa you can click on the design name when you are on the waves page. Then you take your signal and slide it on waves and rerun simulation

Rbruno
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