Lowering the clock frequency for my circuit in Vivado

Question

I have a circuit like this

module control(input clk, output out);
  reg [63:0] r0 = 1, r1 = 2, r2 = 3, r3 = 4, r4 = 5;
  always @ (posedge clk)
  begin
    
    // some logic with a high delay -- representative of my actual project
    r0 <= (r0 + r1 * r2 % (r3 + 1)) % (r2 + 1) % (r4 + 1) + 2;
    r1 <= (r0 + 1) * (r1 + 1) * (r2 + 1) * (r3 + 1) * (r4 + 1) + 2;
    r2 <= r0 + r1 + r2 + r3 + r4;
    r3 <= r0 + 23;
    r4 <= r4 + 1;
    
  end
  assign out = |(r0 + r1);
endmodule

with these constraints

set_property PACKAGE_PIN L1 [get_ports out]
set_property IOSTANDARD LVCMOS33 [get_ports {out}]

set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10 -waveform {0 5} [get_ports clk]

When I let Vivado synthesize and implement this, I get Worst Negative Slack of -262.452 ns, which of course means that the timing constraints are not met.

So the core of my question is: How can I relax the timing constraints? Meaning: How can I let my circuit run at a lower frequency?

My Situation

my FPGA board has a 100 MHz clock which I'm using in the above
I do not need to run my circuit at anywhere near 100 MHz. Even 100 kHz would be fast enough for me
I think it could potentially be possible to pipeline my logic so that it runs within the the 10 ns timing constraint, but I want to avoid this if possible because it would make the circuit more complicated

What I've Tried

I've tried having a register with a counter which I increment by one in every clock cycle and so that I do the actual logic only at one specific value of the counter -- effectively decreasing the frequency. However, Vivado still thinks that the entire logic has to complete in one clock cycle, so it reports the same negative slack as before.
I've tried increasing the clock period in the constraint file -- that made Vivado think that there is more time for the logic to complete so that the timing constraints could seemingly be met, but actually when I tested it on the real hardware, the circuit was still being fed the original 100 MHz clock.

What is the easiest or most standard way to use a lower frequency clock?

Morten Zilmer · Answer 1 · 2022-04-21T04:43:55.457

Multi-cycle path timing constraints for that circuit is a possibility.

The overall design will then still run at 100 MHz clock, but the specific circuit is given multiple cycles for propagation through the combinatorial circuit, while still getting a correct timing analysis that it can close timing within the number of cycles you have manually given for the circuit.

You will then have to make a start signal, asserted a single 100 MHz cycle, to load in the new arguments, and a done signals, also asserted a single cycle, to capture the result.

You must ensure a match between the cycles in the multi-cycle path and the cycles in the design between the start and done pulses.

The details for specifying a multi-cycle patch to Vivado timing analysis can be found in appropriate searches :-)

score 0 · Answer 2 · answered Apr 22 '22 at 13:04

Trace the clock back to its source to find out where it comes from. Many Xilinx designs bring clock into the part and run it to a MMCM (Mixed Mode Clock Manager) to generate the local clock. The MMCM can generated in Vivados IP generation tool (IP Catalog). It has parameters for the clock or clocks it generates. Change those parameters to meet you requirements.

It will have a minimum frequency it can generate, you will need to understand its operation in order to make the change. The minimum clock frequency it can generate will depend on its input clock from the board input. It also has a minimum frequency it can accept from the board edge, that will be in the low MHz range depending on the family, part, and speed grade.

You can learn a lot by opening Vivado and starting a new IP project, then selecting MMCM to see how it works. There are some related Xilinx primitives involved such as bufg's. Its helpful to understand what bufg's are and how they are used.

More info on 7-Series clocking here:
https://docs.xilinx.com/v/u/en-US/ug472_7Series_Clocking

It a good idea to study the clock scheme for any FPGA you work on so that you understand where and how the clock is generated.

Lowering the clock frequency for my circuit in Vivado

My Situation

What I've Tried

2 Answers2