Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

Xilinx, Inc.
Altera Corp. (now Intel FPGA)
Atmel Corp. (now Microchip Technology Inc.)
Lattice Semiconductor Corp.

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions

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1 answer

Convert 32-bit hex value int to four 8-bit bytes from file read

I am trying to read in a hex file that is n lines long, with each line consisting of a 32-bit hex value. I then need to take the 32-bit hex values and turn them into 8-bit bytes to be used in a memory model. I am able to open the file and loop…

verilog system-verilog fpga

asked Jul 26 '22 at 19:49

rt0218

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1 answer

Is it synthesizable, using integer variable for the for-loop within a generate block in a always block?

In the code below, the line: mem_reg[wr_cmd_addr[SEG_ADDR_WIDTH*n +: INT_ADDR_WIDTH]][i*8 +: 8] <= wr_cmd_data[SEG_DATA_WIDTH*n+i*8 +: 8]; The index "i" is an integer type. It is being synthesized right?? I was under the impression that integer…

for-loop verilog fpga hdl generate

asked Jul 19 '22 at 00:25

AZ123

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0 answers

Power of 3 of a Binary Number in GF(2^6) in VHDL?

I tried myself in a GF(2^4). With the minimal polynom z^4+z+1: a(z) = a0 + a1.z + a2.z^2 + a3.z^3 [a(z)]^3 = a0 + a1.z^3 + a2.z^6 + a3.z^9 = a0 + a1.z^3 + a2.(z^3 + z^2) + a3.(z^3+z) = a0 + a1.z + a2.z^2 + (a1+a2+a3).z^3 Now i have to replace (a0,…

math fpga galois-field

asked Jul 18 '22 at 21:25

Sir Kadse

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1 answer

Where does Vivado reference primitives when building the implemented design?

I'm trying to figure out exactly what file vivado uses to create the attributes of a primitive block. I'm trying to do an experiment with removing some of the properties but no matter what file I edit they always reappear after implementation.…

fpga hdl vivado

asked Jul 14 '22 at 22:44

WaterStopperN

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2 answers

How do i get a 100kbps clock for an I2C on Quartus Prime?

I am doing a university project in which i have to build a I2C which have only one slave and will have to transmit a data with 5 bits, 4 bits for the number which is in the range of 0 to 9 and 1 bit to read or write, i'm using a DE10-LITE with VHDL…

vhdl hardware fpga intel-fpga

asked Jul 09 '22 at 20:50

Lucca Machado

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1 answer

Declaring variables in Verilog for loop

I've been trying to wrap my head around how for loops are simulated and synthesized in Verilog, but there's one aspect I've noticed that I can't quite understand. It seems that when variables are declared from within a for loop, only one variable is…

verilog fpga

asked Jul 07 '22 at 23:45

Ewen Crawford

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1 answer

Strange VHDL behavior on hardware unlike simulation

I have a simple VHDL code which has two process. The second process updates the output port m_LED based on the state CF value. In simulation I see the behavior as expected. But when I program the FPGA I noticed that, the output port m_LED is…

vhdl fpga modelsim

asked Jul 05 '22 at 01:07

karthik

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1 answer

VHDL - access to 2D array of std_logic_vectors gives unexpected bus conflict

Background: I'm working on a generic systolic array. I created an entity called "systolic_row" to create one row of the systolic array. The data is handed from one row to the next using an array of std_logic_vectors (type "row_exchange_array"). This…

vhdl fpga modelsim

asked Jul 04 '22 at 13:47

TomS

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1 answer

HDL Generating Comparison between Matlab HDL Coder and Xilinx Vitis HLS

We're considering the approach on a new project. Our target is developing image processing algorithms and implement them on FPGAs. Matlab HDL Coder converts matlab code to HDL code, and Xilinx Vitis HLS synthesizes C/C++/SystemC to HDL code. We can…

matlab simulation fpga xilinx hdl

asked Jun 29 '22 at 14:31

Hai Pham

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2 answers

How to connect a modport interface to a module that wasn't originally declared using the modport

I have a module that I wrote originally like so: module design_name #( parameter AWIDTH = 32, parameter DWIDTH = 32, ... ) ( input wire clk, input wire rst, input wire [AWIDTH-1:0] write_addr, ... ); // logic, etc. endmodule I now,…

verilog system-verilog fpga hdl vivado

asked Jun 24 '22 at 14:06

joshgalv

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2 answers

SystemVerilog Assertion does not fail when it should

I have a simple assertion as follows: $rose(req) |=> !req[*1:10] until ack ##1 !ack; As I understand, on detection of $rose(req), the assertion should check for !req to be low consecutively for max 10 clocks OR -until- ack arrives (ack=1). Once ack…

fpga register-transfer-level system-verilog-assertions asic

asked Jun 22 '22 at 17:14

CCRCCR

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1 answer

fpga_loadbitstream: Wrong bitstream ID for this device...: Bitstream ID xc7z010clg400-1, current device ID 0/7z010

I am trying to use f4pga to compile one of their examples in f4pga-examples from verilog into a bitstream and run it on my ZYBO Zynq 7000, following the instructions here: https://f4pga-examples.readthedocs.io/en/latest/running-examples.html (Note…

fpga

asked Jun 21 '22 at 18:52

Daniel

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1
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1 answer

Cannot export QNN brevitas to ONNX

I have trained my model as QNN with brevitas. Basically my input shape is: torch.Size([1, 3, 1024]) I have exported the .pt extended file. As I try my model and generate a confusion matrix I was able to observe everything that I want. So I believe…

python machine-learning pytorch fpga onnx

asked Jun 14 '22 at 18:56

MrFoxs

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1 answer

Arrived floor signal is one tick clock too far

I'm working on elevator code in VHDL and I have an issue with signal (przybycie) that shows elevator arrived to choosen floor. There is a code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use…

vhdl fpga state-machine xilinx

asked Jun 09 '22 at 09:56

Saran12

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1 answer

What can I do when my verilog code worked in Simulation and online debugging with ILA but not barely on FPGA?

I am using Verilog to write a quite simple UART send demo. This demo will send out a number after certain seconds. Say the first time it will be 0x00 and the second time it will be 0x01. Every time it will add up one on the previous number. I used…

verilog fpga uart

asked Jun 06 '22 at 07:51

SONGYJ

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