Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

Xilinx, Inc.
Altera Corp. (now Intel FPGA)
Atmel Corp. (now Microchip Technology Inc.)
Lattice Semiconductor Corp.

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions

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1 answer

FFT IP Core - the results of Matlab and FFT IP Core didn't match?

I asked this while back in Xilinx Forum but I got no help, still need the help that's why am asking here. I am working on FFT IP Core to match its result with Matlab. I created an RTL Kernel(XO) using Vivado contains just FFT IP Core, and below u…

fft fpga xilinx

asked Mar 28 '23 at 14:28

A.A.

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1 answer

Clocking Block Cycle Delay Problem in SystemVerilog

I have a stuck Clocking Block in SystemVerilog that i try to understand but I could not. I have just a normal Clocking Block like this, and I just drive one signal to understand. `timescale 1ns/100ps module quiz(); bit clk; logic reset; …

system-verilog fpga test-bench

asked Mar 28 '23 at 12:37

Duy Mạnh NGUYỄN

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1 answer

STA of 2 clocks with the same frequency

Imagine a design has 2 input clocks. They have the "same" nominal frequency but originate from 2 different sources and therefore are asynchronous to each other. The clocks are defined as follows: create_clock -name {clock_a} -period 10.000 -waveform…

fpga vlsi asic

asked Mar 22 '23 at 22:01

shaiko

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0 answers

Convert Simulink model from Altera/Intel DSP Builder to Xilinx/AMD System Generator

I have an old Cyclone III FPGA design for which some blocks are designed using DSP Builder blockset in simulink. As per the new requirement I am to convert this model for the Spartan 7 FPGA using Xilinx System Generator. Is there a way or method to…

matlab simulink fpga

asked Mar 21 '23 at 02:52

Saumil

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0 answers

2nd CMAC device in OpenNIC doesn't get initialized in DPDK

I am trying to use both the devices provided in OpenNIC shell with DPDK. However setting the registers as mentioned in the docs, only the first device is used and the other doesn't get initialized. Logs from EAL: `EAL: Detected 128 lcore(s) EAL:…

fpga xilinx dpdk

asked Mar 18 '23 at 04:48

Ayush

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1 answer

Using keyword `all` in a sensitivity list of a clocked VHDL process

I would like to present the following two versions of VHDL code for a flip flop. Clock and reset in the sensitivity list of the clocked process: library ieee; use ieee.std_logic_1164.all; entity example_ff_clk_rst is port ( i_clk : in …

vhdl hardware fpga

asked Mar 17 '23 at 13:37

jakeh12

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2 answers

How setup- and hold times affect the functionality of the FPGA implementation?

I am currently working on a VHDL module that first reads in the given input data in parallel via a shift register and then outputs the stored data bit by bit at the output in each clock cycle. For this I implemented a state machine that generates an…

vhdl hardware fpga digital

asked Mar 14 '23 at 13:05

RatbaldMeyer11235

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0 answers

Test external peripherals using SDK vitis

I want to test the functioning of a camera ov7670 on my zedboard i linked the carte to a screen using VGA cable . Is it possible to test my design after generating the wrapper on SDK VItis or do i need to install patches ?

sdk camera fpga vga

asked Mar 14 '23 at 12:41

Thabet thabet

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1 answer

Trying to find an error in my VHDL Code, with no luck

There is syntax error that I cannot understand. process(clk) on line 166 of the code the error showing up is Error: Syntax error near 'process' , i'm pretty sure i've checked the code before this line, no matter what i put inside the brackets i get…

sql vhdl fpga

asked Mar 11 '23 at 21:48

Taksiepacze

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0 answers

How to write in a block memory in vivado

In order to display an image from fpga ZedBoard to the screen through VGA interface, I created a dual block memory to store an image and read it from that memory to display it. I dont know how to acces this memory and how to write image in it. This…

memory fpga vga

asked Mar 09 '23 at 14:05

Thabet thabet

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1 answer

Division in Verilog and Q factor representation

I am currently working on a design of an algorithm for signal processing. I created a model in software that appears to work fine and I am now trying to translate it to verilog. Below is what I do in the software. I get a 16 bit input, I do the…

verilog signal-processing fpga xilinx fixed-point

asked Mar 06 '23 at 17:17

user2532296

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0 answers

How to parse a new device tree BLOB in a kernel module?

I am building a kernel module for PCIe device on Linux v5.15.60 on x86. This module connects to my FPGA (containing multiple soft cores) and creates a platform_device. For an other driver to use it. The FPGA embed its own device tree blob in a…

linux-kernel fpga kernel-module device-tree pci

asked Mar 02 '23 at 14:07

cykoenig

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1 answer

How to change the MAC adress of FPGA ZedBoard

How can I assign different MAC addresses to the FPGA? Currently all the ZedBoards have the same default MAC addresses. I'm using PetaLinux and my FPGA ZedBoards boot from SD card.

fpga mac-address zynq petalinux

asked Mar 02 '23 at 08:55

Thabet thabet

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1 answer

How to implement two symmetrical inverter chains on Xilinx FPGA with place and route?

I want to implement two symmetrical inverter chains on Xilinx FPGA. But if I use the automatic layout place and route, the delay of the inverter chains will be more different than each other. The Vivado EDA tool allows me to place and route the LUTs…

simulation fpga xilinx vivado

asked Mar 02 '23 at 01:16

jiacheng hao

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1 answer

if-else condition for custom libraries in VHDL

I want to make two FPGA builds using the same source code but with a slight variation. The variation is defined in terms of a constant defined in the library file. Some instances are enabled or disabled based on this setting. For one build I need…

vhdl fpga hdl vivado

asked Mar 01 '23 at 17:11

surabhig

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