How to write in a block memory in vivado

Question

In order to display an image from fpga ZedBoard to the screen through VGA interface, I created a dual block memory to store an image and read it from that memory to display it. I dont know how to acces this memory and how to write image in it.

This is instanciation from the top_module:

entity top_module is
    Port ( 
        clk100        : in    STD_LOGIC;
        vga_red      : out   STD_LOGIC_VECTOR(3 downto 0);
        vga_green    : out   STD_LOGIC_VECTOR(3 downto 0);
        vga_blue     : out   STD_LOGIC_VECTOR(3 downto 0);
        vga_hsync    : out   STD_LOGIC;
        vga_vsync    : out   STD_LOGIC
        
    
     );
end top_module;

architecture Behavioral of top_module is

    

component clocking
port
 (-- Clock in ports
  CLK_100           : in     std_logic;
  -- Clock out ports
  CLK_50          : out    std_logic;
  CLK_25          : out    std_logic
 );
end component;

    

    COMPONENT blk_mem_gen_0
    PORT (
        clka  : IN  STD_LOGIC;
        wea   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
        addra : IN  STD_LOGIC_VECTOR(18 DOWNTO 0);
        dina  : IN  STD_LOGIC_VECTOR(11 DOWNTO 0);
        clkb  : IN  STD_LOGIC;
        addrb : IN  STD_LOGIC_VECTOR(18 DOWNTO 0);
        doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
    );
    END COMPONENT;

    COMPONENT capture
    PORT(
        pclk : IN std_logic ;        
        addr  : OUT std_logic_vector(18 downto 0);
        dout  : OUT std_logic_vector(11 downto 0);
        we    : OUT std_logic
        );
    END COMPONENT;

    COMPONENT vga
    PORT(
        clk25     : IN std_logic;
        vga_red   : OUT std_logic_vector(3 downto 0);
        vga_green : OUT std_logic_vector(3 downto 0);
        vga_blue  : OUT std_logic_vector(3 downto 0);
        vga_hsync : OUT std_logic;
        vga_vsync : OUT std_logic;
        
        frame_addr  : OUT std_logic_vector(18 downto 0);
        frame_pixel : IN  std_logic_vector(11 downto 0)         
        );
    END COMPONENT;
    
    signal frame_addr      : std_logic_vector(18 downto 0);
    signal frame_pixel     : std_logic_vector(11 downto 0);

    signal capture_addr    : std_logic_vector(18 downto 0);
    signal capture_data    : std_logic_vector(11 downto 0);
   signal capture_we      : std_logic_vector(0 downto 0);
    signal resend          : std_logic;
    signal config_finished : std_logic;
    
    signal clk_feedback  : std_logic;
    signal clk50u        : std_logic;
    signal clk50         : std_logic;
    signal clk25u        : std_logic;
    signal clk25         : std_logic;
    signal buffered_pclk : std_logic;
    
begin
  

    Inst_vga: vga PORT MAP(
        clk25       => clk25,
        vga_red     => vga_red,
        vga_green   => vga_green,
        vga_blue    => vga_blue,
        vga_hsync   => vga_hsync,
        vga_vsync   => vga_vsync,
        frame_addr  => frame_addr,
        frame_pixel => frame_pixel
    );

fb : blk_mem_gen_0
  PORT MAP (
    clka  => CLK50 ,
    wea   => capture_we,
    addra => capture_addr,
    dina  => capture_data,
     
    clkb  => CLK50,
    addrb => frame_addr,
    doutb => frame_pixel
  );
  
capture: ov7670_capture PORT MAP(
        pclk  => CLK50 , 
        addr  => capture_addr,
        dout  => capture_data,
        we    => capture_we(0)
    );
  


your_instance_name : clocking
  port map
   (-- Clock in ports
    CLK_100 => CLK100,
    -- Clock out ports
    CLK_50 => CLK50,
    CLK_25 => CLK25);

end Behavioral ;