I have a stuck Clocking Block in SystemVerilog that i try to understand but I could not. I have just a normal Clocking Block like this, and I just drive one signal to understand.
`timescale 1ns/100ps
module quiz();
bit clk;
logic reset;
default clocking cb @(posedge clk);
default input #1step output #5;
output reset;
endclocking
always #5 clk = ~clk;
initial begin
cb.reset <= '0;
##2 cb.reset <= '1;
##3 cb.reset <= '0;
end
endmodule
As I expected that after first rising_edge clk + 5ns, reset will turn from X to 0. Then reset = 0 will last for next 2 rising_edge. At that time + 5ns, reset will turn from 0 to 1 and last for next 3 rising_edge. But it doesn't work like i thought, reset = 0 only lasted for a single rising_edge. Otherwise that reset = 1 still lasted for 3 rising_edge.
In fact, I have already found how to fix this problem, just by adding @(cb) in the very beginning of "initial block" so it will be:
initial begin
@(cb);
cb.reset <= '0;
##2 cb.reset <= '1;
##3 cb.reset <= '0;
end
After i added that, It will run as I expected. But in the understanding problem, I still have no idea, what is going on? What is mission of "@(cb)", this problem causes because of my code or compiler???. I would be appriciated, if someone can explain in detail. Thanks