Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

Xilinx, Inc.
Altera Corp. (now Intel FPGA)
Atmel Corp. (now Microchip Technology Inc.)
Lattice Semiconductor Corp.

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions

votes

0 answers

Why does state instantly go to last state whenever pushbutton is pressed

I am implementing a door lock that requires user password. I have implemented states to identify predefined passwords of 123, 122, and 121, and it unlocks the door after the correct password is entered sequentially. I am implementing this door lock…

asked Jun 17 '23 at 15:03

IRFAN AZEEZ

votes

0 answers

Vitis linking error "[CFGEN 83-2229] Failed to find single interface to reach all segments in {HP!, HP0, HP2}"

i am using the Kria Robotics Stack with Vitis 2022.1 to accelerate my ROS2 nodes on the KR260. Using OpenCL C Kernels, i am trying to connect the kernel ports to AXI-Interfaces to access global memory in parallel. For example i have three kernel…

opencl fpga xilinx hardware-acceleration ros2

asked Jun 14 '23 at 15:54

mirhad

votes

1 answer

FPGA Max 10 DE10 Lite Board Error (169026) on Quartus 22.1 VHDL

I am trying to implement the project https://www.youtube.com/watch?v=50EC76bpkQI When I try to compile the Quartus II, it gives me the following errors: Error (169026): Pin myLEDR[1] with I/O standard assignment 3.3-V LVTTL is incompatible with I/O…

fpga quartus

asked Jun 12 '23 at 16:20

james

votes

0 answers

How to generate a clean clock signal for an ADC from a Spartan-6 SLX9 FPGA?

I'm working on a project where I need to drive an ADC with a clock signal generated by a Spartan-6 SLX9 FPGA. However, the clock signal isn't well and the output of ADC is noisy, and we've identified that the noise is coming from the FPGA. We tried…

fpga adc

asked Jun 08 '23 at 06:17

Md.shah

votes

0 answers

How do I read data from a register on an FPGA board using PySerial?

I have implemented a simple lock in amplifier on an FPGA board, and I'm writing the detected amplitude to a register on the board. I'm then using a microprocessor to read from the register while the processor itself is connected to my laptop via…

serial-port fpga pyserial uart cpu-registers

asked Jun 01 '23 at 15:16

Merkel_Bot

votes

2 answers

How to Read Data from a specific address of the FPGA QSPI Flash board?

I'm new to Vitis and XilinX-edk world. I'm working on a project and i want to implement a design that uses microblaze to do these 3 tasks : 1-Read some data from a specific QSPI Flash address. 2-Save into the BRAM. 3-Wait for 1 in a GPIO Input then…

fpga xilinx spi microblaze xilinx-edk

asked May 25 '23 at 13:41

mohamed AFASSI

votes

1 answer

What value do uninitialized internal signals take on when when used in signal assignment?

In the following code, A is attached to I/O while B is an internal signal that is not assigned an initial value. architecture Behavioral of adder is signal B : STD_LOGIC_VECTOR(7 DOWNTO 0); begin process(clock) variable result :…

vhdl fpga

asked May 24 '23 at 21:18

cepuz

votes

2 answers

How to split code and data into 2 different ELF files?

I have a code for an embedded microncontroller in an FPGA that contains variables stored in the stack and I would like to seperate the code from those variables and put those into 2 ELF files. The goal in the end is to convert the ELF files into…

c gcc embedded fpga linker-scripts

asked May 22 '23 at 20:47

cfl

votes

1 answer

non-blocking assignments with if statements

A bit confused about how Verilog interprets this code block and how it is synthesized in FPGA. ... data_reg[bit_count] <= rx; bit_count <= bit_count + 1; if (bit_count == 7) begin bit_count <= 0; end ... The question is: if bit_count == 7 does…

verilog fpga

asked May 22 '23 at 17:02

user529327

votes

2 answers

CLOCK_DEDICATED_ROUTE error in creating an RS latch

I am trying to describe a RS asynchronous latch in VHDL. I receive this error from vivado. [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the…

vhdl fpga vivado intel-fpga flip-flop

asked May 18 '23 at 14:02

Marcu Petric

votes

1 answer

Altera Quartus II Can't synthesize current design -- Top partition does not contain any logic

I've started working with FPGAs and VHDL In Model Sim everthing works and does what it has to do, but if I want to compile it in Quartus the error shows up. library ieee; use ieee.std_logic_1164.all; entity fpga_aufgabe1 is end…

vhdl fpga quartus

asked Apr 26 '23 at 16:50

Setes

votes

1 answer

Can synthesizers pay attention to intentional 'Z' at compile time?

In Verilog, I have an input port that I would like to make optional. It's the start pin for a microarchitecture. If user does not want to drive the start pin manually, the module will use its own internal clock to drive the start pin. It would be…

verilog vhdl fpga synthesis

asked Apr 16 '23 at 13:46

James Strieter

votes

1 answer

How to use XADC's GPIO on Xilinx KC705 FPGA

I output the clock generated through GPIO, but I cannot check the data on the oscilloscope. I am developing using the AMD Kintex7 FPGA KC705 Evaluation Kit and using the Vivado 2022.2 version. I want to use the GPIO of XADC and output the created…

verilog fpga gpio xilinx

asked Apr 14 '23 at 10:52

Jihun Kim

votes

1 answer

couldn't implement registers for assignments on this clock edge(VHDL)

``--! start state logic start_int <= start; ssl_edge_detect_proc: process(start_int,clk) begin if rising edge(start_int) then start_edge_old<='1'; else start_edge_old<='0'; end if; start_edge<=start_edge_old; end…

vhdl fpga modelsim quartus

asked Apr 11 '23 at 08:01

Srikanth

votes

1 answer

Yosys optimizes GPIO RX module away

I recently started playing with the iE40 icestick evaluation board. I encountered what I think is strange behavior: It seems that Yosys wants to optimizes away a module which takes a port connected to a RX gpio pin. IMO this should never happen as…

verilog fpga lattice hdl yosys

asked Apr 09 '23 at 18:52

Cornelius Korinthia

Prev 1 2 3

…

99 100 Next