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I want to implement two symmetrical inverter chains on Xilinx FPGA. But if I use the automatic layout place and route, the delay of the inverter chains will be more different than each other. The Vivado EDA tool allows me to place and route the LUTs and DFFs manually. But I don't know how to ensure that they are symmetrical. Just make sure they are in symmetrical position? And how about the wires? The wires are always very messy. Is there any solutions?

I try to place the LUTs and DFFs manually, but I dont know if they are already symmetrical. I want some directives or some examples to deal with it. I want the two inverter chains to have smaller difference in delay in post implementation simulation and on board running than automatic layout place and route.

Mikef
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jiacheng hao
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1 Answers1

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Look at the 'BEL' (Basic Element) placement constraint. This allows you to exactly place individual elements such as inverters in precise x-y CLB/Slice locations. This will remove any variable build-build variation and guarantee more predictable and expected place and route.

For your need avoid any 'pblock' constraints in Vivado as these are more general geometric constraints that will still result in some variation and your two inverter chains won't be close build-build.

Be aware that due to minor fabrication issues all transistors in your given device will have some variation. You may need to exhaustively characterize BEL-constrained inverter chains to get the right combination of elements that are more symmetric.

911c4s991
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