if-else condition for custom libraries in VHDL

Question

I want to make two FPGA builds using the same source code but with a slight variation.

The variation is defined in terms of a constant defined in the library file. Some instances are enabled or disabled based on this setting.

For one build I need something like this: constant CONFIG_EN : std_logic_vector(3 downto 0) := "1001"

and the other build I need this setting: constant CONFIG_EN : std_logic_vector(3 downto 0) := "1111"

What is the best way to implement it?

Can I do something like the following in the library file?:

-- User-defined before each build
build1 = 0 

if(build1) then
   constant CONFIG_EN : std_logic_vector(3 downto 0) := "1001"
else
   constant CONFIG_EN : std_logic_vector(3 downto 0) := "1111"

If no, what is the best way to go about this?

What do you mean by library file? Do you mean a VHDL package compiled into a library? Also are you using Vivado in project mode (GUI) or non-project mode (script)? Are you willing to implement a tcl or bash or csh script based answer? Don't answer in the comments, add your answers as more information to the question. — Mikef, Mar 01 '23 at 19:49
All synth tools I know allow you set generics on the top level. It sounds like this might be the most appropriate in your situation. — Tricky, Mar 01 '23 at 23:18
Using subjective criteria ("best way") opens a question to opinion based answers. — user16145658, Mar 01 '23 at 23:55

Jim Lewis · Accepted Answer · 2023-03-01T20:00:22.540

Define it in package.

File: ConfigPkg_build1.vhd

package ConfigPkg is
   constant CONFIG_EN : std_logic_vector(3 downto 0) := "1001" ;
end package ConfigPkg ;

File: ConfigPkg_build2.vhd

package ConfigPkg is
   constant CONFIG_EN : std_logic_vector(3 downto 0) := "1111" ;
end package ConfigPkg ;

Then let your compile scripts decide which file to compile based on which build you are using.

Alternately, you can use a generic on the design to specify which build you are using. The code below gives you an idea of how to handle this.

entity top is
  generic (BUILD: integer) ;
  port ( . . . ) ; 
end entity top ;
architecture struct of top is 
  function IfElse (Sel : boolean ; A, B : std_logic_vector) return std_logic_vector is 
  begin
    if Sel then 
      return A ; 
    else 
      return B ; 
    end if ; 
  end function IfElse ; 

  constant CONFIG_EN : std_logic_vector(3 downto 0) := IfElse(BUILD = 1, "1001", "1111") ; 

begin 
  . . .

I would probably use the package based approach. The generic approach requires that you specify the generic value somewhere - potentially on the tool command line.

I should also note that VHDL-2019 supports conditional expressions and conditional analysis (compilation). With conditional expressions we will not need the function IfElse. Be sure to tell your vendors you want them to implement VHDL-2019. From a simulation perspective, Aldec has implemented much of VHDL-2019, other commercial vendors seem to be lagging behind.

if-else condition for custom libraries in VHDL

1 Answers1