Using keyword `all` in a sensitivity list of a clocked VHDL process

Question

I would like to present the following two versions of VHDL code for a flip flop.

Clock and reset in the sensitivity list of the clocked process:

library ieee;
use ieee.std_logic_1164.all;

entity example_ff_clk_rst is
    port (
        i_clk  : in  std_logic;
        i_rst  : in  std_logic;
        i_data : in  std_logic;
        o_data : out std_logic
    );
end example_ff_clk_rst;

architecture rtl of example_ff_clk_rst is

    signal s_ff_q, s_ff_d : std_logic;

begin

    s_ff_d <= i_data;

    process(i_clk, i_rst)
    begin
        if i_rst = '1' then
            s_ff_q <= '0';
        elsif rising_edge(i_clk) then
            s_ff_q <= s_ff_d;
        end if;
    end process;
    
    o_data <= s_ff_q;

end rtl;

Using keyword all to infer the sensitivity list of the clocked process:

library ieee;
use ieee.std_logic_1164.all;

entity example_ff_all is
    port (
        i_clk  : in  std_logic;
        i_rst  : in  std_logic;
        i_data : in  std_logic;
        o_data : out std_logic
    );
end example_ff_all;

architecture rtl of example_ff_all is

    signal s_ff_q, s_ff_d : std_logic;

begin

    s_ff_d <= i_data;

    process(all)
    begin
        if i_rst = '1' then
            s_ff_q <= '0';
        elsif rising_edge(i_clk) then
            s_ff_q <= s_ff_d;
        end if;
    end process;
    
    o_data <= s_ff_q;

end rtl;

My assumption was that the keyword all can only be used for a combinational process. However, after searching through the IEEE 1076-2008 VHDL LRM, I could not find any such restriction.

Question: Can the keyword all be used in the sensitivity list of a clocked process for synthesis? From asking my colleagues, it works in Intel Quartus. Are there any downfalls to using the keyword all instead of a sensitivity list with clock and reset for clocked processes?

Thank you for your answers.

Synthesis is fine (per @Tricky). A free or low cost simulator that does less optimization may run slower with `all` than with just `clk` and asynchronous control signals. That said, a good optimizing simulator should be fine with `all`. — Jim Lewis, Mar 19 '23 at 21:15

score 3 · Accepted Answer · answered Mar 17 '23 at 13:56

3

The all keyword simply instructs to tool to infer the sensitivity list. So will work fine for any process. Synthesis tools have ignored sensitivity lists for a long time anyway, as they follow template patterns to infer sync vs async logic. They will often indicate when signals are missing from a sensitivity list. Simulators on the other hand simply do as instructed, and only re-evaluate the process on a change in a signal in the list.

answered Mar 17 '23 at 13:56

Tricky

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The idea is post synthesis behavior matches RTL simulation by examining sensitivity lists. IEEE Std 1076.6-2004 RTL Synthesis (withdrawn) 6.2.1 Modeling level-sensitive storage elements 6.2.1.1 Level-sensitive storage from process with sensitivity list "The process sensitivity list shall contain all signals read within the process statement." 6.5 Combinational logic ditto. 8.9.2 Process statement "The sensitivity list shall include those signals or elements of signals that are read by the process except for signals read only under control of a clock edge". The last would not bar **all**. – user16145658 Mar 17 '23 at 22:39

Using keyword `all` in a sensitivity list of a clocked VHDL process

1 Answers1