Stack Overflow
Stack Overflow

Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions
0
votes
1 answer

How do I use clocking wizard to create a slower clock for my program?

Hey guys so I'm very new to Verilog and Fpga's so sorry if I am missing something very simple. I am trying to interface an external SRAM that I would like to test for functionality. I have written this code along with a test bench to verify it. I…
Sephiroth
  • 3
  • 1
0
votes
0 answers

Implementing a simple code in Microsemis Soft Console

I would like to get into the field of FPGAs a bit. I currently have a PolarFire Everest Dev Board and would like to try something small on it for testing purposes. My current level is very low, i.e. complete beginner. My first working project was a…
samitxb
  • 1
  • 2
0
votes
2 answers

VHDL: big slv array slicing indexed by integer (big mux)

I want to slice a std_logic_vector in VHDL obtaining parts of it of fixed dimensions. The general problem is: din N*M bits dout M bits sel clog2(N) bits Expected behaviour in an example (pseudocode): input 16 bit, want to slice it in 4…
dadduni
  • 3
  • 2
0
votes
0 answers

Lattice Diamond programmer, FPGA wont load from flash on power cycle

We have a design that has worked for years when programming with the Diamond WIn7 software. We are using the Advanced FPGA loader feature of the Diamond programming software in WIN10(v.3.12) now. We program the CPLD (LCMXO2-640ZE)with our .JED…
smcmurphy
  • 1
  • 1
0
votes
0 answers

FT2232HQ synchronous FIFO mode is much slower than it should be in Ubuntu

I'm working on a project which needs to collect data from FPGA. I'm using an FTDI FT2232H UART/FIFO IC. According to the datasheet, the chip can transfer up to 40 Mbytes/s in single-channel synchronous FIFO mode. However, when I use the Linux system…
deponce ye
  • 1
  • 1
0
votes
1 answer

I got pin planning errors while generating bitstream, what is the problem here?

While generating bitstream I get following errors: [DRC NSTD-1] Unspecified I/O Standard: 9 out of 14 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or…
sali
  • 1
  • 1
0
votes
2 answers

Get IEEE-754 single precision representation of a real number in VHDL

I want to convert a real number to his bit representation, with the fields of sign, exponent and mantissa in a VHDL TB for testing purposses (as a STD_LOGIC_VECTOR of 32 bits). Is there anyway to convert a real number to this representation directly…
Diego Ruiz
  • 187
  • 2
  • 11
0
votes
1 answer

Delay a 32-bit signal with N clock cycle in verilog

I am trying to delay a 32-bit signal using shift register. My logic is a single flip flop delay a signal by 1 clk so I use shift register as it is combination of flip flop can someone guide me what is wrong with this code. module delay_n_cycles ( …
hope_99
  • 27
  • 5
0
votes
1 answer

Error running 'make DETECT_DEVICES' on Intel FPGA Monitor Program

I'm currently trying to run ARM assembly on my DE series board. However when I try to open my project I get the following error on the Intel FPGA Monitor Program: Error running 'make DETECT_DEVICES'. (java.io.IOException: The pipe is being…
Emre Türker
  • 45
  • 5
0
votes
1 answer

Vivado HW manager does not detect my ARTY A7

I installed Vivado(2022.2) ML Standard with all the drivers on Windows 10. As I try to auto or manual connect ARTY A7 in Vivado hardware manager the device doesen't show up. What I tried: Changed USB cable, Connect device to other PC, where it is…
Matevž Ves
  • 13
  • 5
0
votes
0 answers

GPUDirect RDMA out of range pin address by Quadro p620

I want to implement FPGA-GPU RDMA by nvidia quadro p620. Also, I used common PCIe BAR resources(BAR0 - BAR1 - BAR2) for FPGA registers and other chunk controllers handling which is independent from RDMA in my custom driver. PCIe managements are OK…
SkyCyborg
  • 1
  • 2
0
votes
1 answer

How can I use GCC to compile a binary file which can be used for my FPGA,where I have used verilog to synthesis

First I synthesized a CPU that supports RISCV32IM using verilog, but I can't test if the CPU is working properly. I hope a compiler(such as GCC) can generate instructions to help me test, but normal compilers can only generate EXE files that require…
linchi li
  • 1
0
votes
0 answers

Unable to assign counter signal to output (FSM)

I'm working on an FSM for a quadrature encoder counter, to be used on the Arty A7 35 --- this is my first VHDL project, so I apologize if I am missing something very basic. I have an internal count signal that I decrement or increment in the FSM,…
Wally
  • 11
0
votes
1 answer

QUESTA + Modelsim using using command Gate Level Simulation

I have installed Quartus V20 + ModelSim V20. It's the first time I use that. I have buyed a book to try to understand how to simulate / use a FPGA system. I have done a simple cirtuit to check the delay and glich of the gate. Circuits characteristic…
user3514930
  • 1,721
  • 1
  • 9
  • 7
0
votes
1 answer

How to loop for a variable amount in verilog?

In any hardware definition language, I know we can't declare a loop to loop over some circuits for some variable n times, instead we need to loop for a fixed value. So I wanted to ask, if I have the following snippets of code: I'm writing some sort…
need_help_ples
  • 53
  • 7
1 2 3
…
99 100