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In Verilog, I have an input port that I would like to make optional. It's the start pin for a microarchitecture. If user does not want to drive the start pin manually, the module will use its own internal clock to drive the start pin.

It would be really nice if the user could hard code this pin to 'Z', and then the module has a snippet like this:

always @(posedge clk) begin 
  if (rst == 1'b1) begin 
    ...
  end else begin 
    if (start == 1'bz) begin 
      start_2 <= internally_generated_strobe;
    end else begin 
      start_2 <= start;
    end
  end
end

The port map to instantiate this module has something like this:

my_module INST_NAME (
  .clk(clk),
  .rst(rst),
  .start(1'bz),
  ...
  );

Is this something that most synthesizers support? Or will you get weird results?

I give this example in Verilog, but I'm also interested if VHDL vs. Verilog makes any difference.

Tricky
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James Strieter
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  • in verilog standard z or x are treated as '0' in many cases. Most likely this will be the situation in your example. In some other cases it can tell synthesizer that it is free to chose between 0 and 1. And in case of buses, a synthesizer might use it to generate bus controls. However, check errors and warnings in the log first. It should tell you something about this. – Serge Apr 16 '23 at 20:00
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    Why don't you have an I/O cell with either a weak pull up or pull down to the inactive state and logically OR the two? – user16145658 Apr 17 '23 at 01:34
  • @user16145658 Because the port is a strobe, not DC. By default, I want to strobe that signal every 100 clocks for example, but if the user wants to strobe that port at a different frequency I want to make it easy to do so. – James Strieter Apr 18 '23 at 01:08
  • Provide more info. You're asking your readers to play 20 questions. – user16145658 Apr 18 '23 at 01:15
  • @user16145658 I'm not asking users to solve the problem. I'm asking if a very specific approach will work. – James Strieter Apr 18 '23 at 01:39

1 Answers1

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There is no such thing as an X or Z state in real hardware, it is an abstract created by digital discrete simulation. In real hardware, a signal is has an analog voltage with a threshold that gets treated as a 0 or 1.

It's possible to create an analog circuit that could detect if a signal undriven, but no digital synthesis can do this.

What you can do is write a description that assigns a signal to an X state, and the synthesis tool will treat that as a "don't care" and create logic that assigns the signal to a 0 or 1 state; whichever state reduces the amount of hardware needed. A synthesis tool cannot create hardware that IS the X state nor can it create hardware that can detect an X state.

You can all write a description that assigns a signal to a Z state so that another assignment statement to the same signal can drive a 0 or 1 state. A synthesis tool will create hardware that turns off the driver to that signal, but the signal will eventually resolve to a 0 or 1 state depending on the presence of other active drivers on the signal, or the charge decay time of the wire.

For simulation debug, you can write a description that checks if a signal has been assigned the X or Z state using the identity operators === and !==, but no synthesis can create hardware that detects that because it does not exist in hardware. It will generate an error if you try.

dave_59
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  • "No such thing". Not quite true. You can *drive* 'Z' on an output pin, e.g to let another chip drive it. However as you say, you can't *test* a pin for equality with Z, at least not in any FPGA or ASIC. –  Apr 16 '23 at 21:55
  • @user_1818839. It is true. There are no X or Z states in hardware. There are X and Z states in a hardware description language that can be used to represent certain situations like a don't care, or to turn off an I/O pin driver, but you can never make an assignment to a signal with a X or Z value and have a synthesis tool know what to do with it. – dave_59 Apr 17 '23 at 05:33
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    You cannot drive "X". But you CAN drive "Z" which a synth tool does understand, and in the appropriate place (which in recent FPGAs means I/O pins) turns the output off. Internally, in the XC3000 era, you could turn drivers off too; newer FPGAs can't do this, so synthesis will simulate such internal tristates with multiplexers to the extent they can. –  Apr 17 '23 at 11:05
  • @dave_59 Hardware has both X and Z, with X being universally bad, and Z being sometimes good, such as when devices share a bus. But this answer misses the point. Nowhere does my question require that hardware actually realize an X or Z. What I'm really asking is "Does the language give you an error if you set something to Z? And if not, can you exploit that fact to make an input port optional?" – James Strieter Apr 18 '23 at 01:03
  • @JamesStrieter, It is not an error in the language, but a synthesis tool will generate an error if you feed it that. See my updated answer. – dave_59 Apr 18 '23 at 03:11