Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

When asking a question, specify a manufacturer and FPGA model family if applicable.

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Nios ii with FIFO

Does anyone have any ideas how to connect FIFO to Nios 2 in Platform Designer, and how looks like the C code for the processor to write data to FIFO? I'm sorry but I didn't find any information in internet how to do it exactly. everyone only says…
Yura
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FPGA booting from a specified address in a SPI Flash

I am working with lattice crosslink-nx fpga. Recently I had a requirement where I need to boot fpga bitstream from an external SPI flash. But the Bitstream is located in a random address (which is a known address). So in this scenario, can I boot my…
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(VHDL-1154) near 'std_logic_vector' ; type conversion expects one single argument

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.ALL; use ieee.math_real.all; Use IEEE.STD_LOGIC_UNSIGNED.ALL; port ( signal Led_7 : out std_logic := '1'; signal Led_6 …
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Does PicoBlaze have separate flags for each regbank (like Z80), or are the same flags used in both regbanks?

Does PicoBlaze have separate flags for each regbank (like Z80), or are the same flags used in both regbanks? For instance, consider the following code: regbank a load s0, 0 sub s0, 0 regbank b load s0, 1 sub s0, 0 regbank a jump z , success jump…
FlatAssembler
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indexing memory for UART transmission using > 100% SLICEs Tang Nano

I am trying to build a simple UART reception parser command line based on example from Tang Nano 9K repo here, here is my modified version. It basically uses a memory to hold some values, which is working. Once I receive 5 characters I would like to…
mhanuel
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Rocket chip build failing ,shows permission denied error after building rocket tools

I have been trying to build rocket chip ,i have followed all the steps as mentioned on the github repository https://github.com/chipsalliance/rocket-chip , while building the rocket chip tools , i am getting the following error.Did i export the path…
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frequency counter with Lattice ice40 dev board

Hello I am very new to the FPGAs. My goal is to make a frequency counter that would be able to count 5-6Mhz with +-5Hz error. Would Lattice ICE40 be sufficient for this task? This board looks pretty simple to start and not so expensive. Thanks,
Pavs
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Can't add description of customization parameters in Edit Packaged IP of Xilinx Vivado

Settings: Vivado 2023.1 on Windows 10. The customization parameters were added after Create and Package New IP wizard. The Description field of all the newly added customization parameters is always blank. I filled up the Tooltip field in Edit IP…
zzzhhh
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How to port design implementations made on gem5 to a realtime RISCV hardware

I have created a project on gem5 modifying the cache replacement policies I would like to port the design implemented on gem5 to a real-time RISCV processor. How do I do that should I first port it to something like Rocketchip and then port it to an…
user22049227
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Function Wash not increasing value in sec signal in VHDL

I'm very new to VHDL and for my digital design project I have to make a simulation of a washing machine in a DE10-Lite FPGA with finite states. Everything seems good so far but when it's turn for the impure function Wash to work, it looks like…
Adolf RJ
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How to read data from FPGA on HPS side

I am a novice. I have a cyclone V board. I have generated several 32-bit ASCII codes through verilog on the FPGA side. I want to send them to the HPS side through the H2F AXI bus and program the HPS side to read them. . I connected the FIFO and H2F…
2258432
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How to synthesize UDP (User defined primitive) for fpga

I am a newbie with fpga design. I am trying to synthesize a udp file for fpga prototyping. Currently, Vivado and synplify cannot support synthesis for UDP file. Anybody have the solution, please help me ! I intend to create a model for UDP with…
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Synchronizing RPU timer with gPTP clock on Xilinx UltraScale+

I'm working on an application that involves Xilinx UltraScale+ SoC, where the APU runs Linux and the system clock is synchronized with the gPTP (Generalized Precision Time Protocol) clock. My goal is to run a software application on the RPU…
user1020828
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PS to PL on the X410

I have a few questions regarding the USRP X410 and wanted to see if anyone else has ran into the same issue. To test out the product, I have created a program that will generate a random number, I have also made a bitstream to do some operations on…
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How to calculate Setup slack and Hold slack?

I'm having trouble understanding how to calculate Setup slack and Hold slack correctly. According to the Intel Quartus Timing Analysis manual, Setup slack is calculated as Data Required Time (Setup) minus Data Arrival Time, and Hold slack is…