I'm working on a project where I need to drive an ADC with a clock signal generated by a Spartan-6 SLX9 FPGA. However, the clock signal isn't well and the output of ADC is noisy, and we've identified that the noise is coming from the FPGA.
We tried using an external clock generator module to generate the clock signal, and the noise decreased significantly. But now we need to generate the clock signal directly from the FPGA to simplify our system.
We've already tried using the ODDR2 and Clock IP cores to generate the clock signal, but the noise is still present.
What other techniques or IP cores can we use to generate a clean clock signal for the ADC from the FPGA? Any tips or recommendations would be greatly appreciated.
