Altera Quartus II Can't synthesize current design -- Top partition does not contain any logic

Question

I've started working with FPGAs and VHDL In Model Sim everthing works and does what it has to do, but if I want to compile it in Quartus the error shows up.

library ieee;
use ieee.std_logic_1164.all;

entity fpga_aufgabe1 is
end entity;

architecture arch of fpga_aufgabe1 is 

  signal s : std_logic_vector(2 downto 0);
  signal a : std_logic_vector(6 downto 0);
  signal b : std_logic_vector(6 downto 0);
  signal c : std_logic_vector(6 downto 0);
  
  signal ar : std_logic_vector(6 downto 0);
  signal al : std_logic_vector(6 downto 0);
  
  signal br : std_logic_vector(6 downto 0);
  signal bl : std_logic_vector(6 downto 0);
  
  signal cr : std_logic_vector(6 downto 0);
  signal cl : std_logic_vector(6 downto 0);
  
  signal a_high : std_logic_vector(3 downto 0);
  signal a_low : std_logic_vector(3 downto 0);
  
  signal b_high : std_logic_vector(3 downto 0);
  signal b_low : std_logic_vector(3 downto 0);
  
  signal c_high : std_logic_vector(3 downto 0);
  signal c_low : std_logic_vector(3 downto 0);
  begin
    
    a_high <= '0' & a(6 downto 4);
    a_low <= a(3 downto 0);
    
    b_high <= '0' & b(6 downto 4);
    b_low <= b(3 downto 0);
    
    c_high <= '0' & c(6 downto 4);
    c_low <= c(3 downto 0);
    
    dekoder_ina1: entity work.fpga_ssd(arch)
      port map (a_low,ar);
    dekoder_ina2: entity work.fpga_ssd(arch)
      port map (a_high,al);
        
    dekoder_inb1: entity work.fpga_ssd(arch)
      port map (b_low,br);
    dekoder_inb2: entity work.fpga_ssd(arch)
      port map (b_high,bl);
    
    
    alu: entity work.fpga_ALU(arch)
      port map (s,a,b,c);
    dekoder_out1: entity work.fpga_ssd(arch)
      port map (c_low,cr);
    dekoder_out2: entity work.fpga_ssd(arch)
      port map (c_high,cl);
        
    
    
    
end arch;

library ieee;
use ieee.std_logic_1164.all;

entity fpga_ssd is 
  port( 
    g:  in std_logic_vector(3 downto 0);
    y:  out std_logic_vector(6 downto 0) ); 
end fpga_ssd;

architecture arch of fpga_ssd is

--  signal zero:  std_logic_vector(6 downto 0)  := "1111110";
--  signal one:  std_logic_vector(6 downto 0)   := "0110000";
--  signal two:  std_logic_vector(6 downto 0)   := "1101101";
--  signal three:  std_logic_vector(6 downto 0) := "1111001";
--  signal four:  std_logic_vector(6 downto 0)  := "0110011";
--  signal five:  std_logic_vector(6 downto 0)  := "1011011";
--  signal six:  std_logic_vector(6 downto 0)   := "1011111";
--  signal seven:  std_logic_vector(6 downto 0) := "1110000";
--  signal eight:  std_logic_vector(6 downto 0) := "1111111";
--  signal nine:  std_logic_vector(6 downto 0)  := "1111011";
--  signal a:  std_logic_vector(6 downto 0)     := "1110111";
--  signal b:  std_logic_vector(6 downto 0)     := "0011111";
--  signal c:  std_logic_vector(6 downto 0)     := "1001110";
--  signal d:  std_logic_vector(6 downto 0)     := "0111101";
--  signal e:  std_logic_vector(6 downto 0)     := "1001111";
--  signal f:  std_logic_vector(6 downto 0)     := "1000111";
--  signal err:  std_logic_vector(6 downto 0)   := "1001001";

begin
  
  
  with g select
    y <= "0000001" when  "0000",
         "1001111" when   "0001",
         "0010010" when   "0010",
         "0000110" when "0011",
         "1001100" when  "0100",
         "0100100" when  "0101",
         "0100000" when   "0110",
         "0001111" when "0111",
         "0000000" when "1000",
         "0000100" when  "1001",
         "0001000" when     "1010",
         "1100000" when     "1011",
         "0110001" when     "1100",
         "1000010" when     "1101",
         "0110000" when     "1110",
         "0111000" when     "1111",
         "0110110" when   others;
end arch;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fpga_ALU is 
  port( 
    s:  in std_logic_vector(2 downto 0);
    
    a:  in std_logic_vector(6 downto 0);
    b:  in std_logic_vector(6 downto 0);
    
    c:  out std_logic_vector(6 downto 0) ); 
end fpga_ALU;

architecture arch of fpga_ALU is
  
  signal a_int: unsigned(6 downto 0);
  signal b_int: unsigned(6 downto 0);
  signal shift: std_logic_vector(6 downto 0);
  signal agb:  std_logic_vector(6 downto 0) := "0000000";
  signal aeb:  std_logic_vector(6 downto 0) := "0000000";
  signal inca: std_logic_vector(6 downto 0);
  signal add: std_logic_vector(6 downto 0);
  signal modulo: std_logic_vector(6 downto 0);
  signal und: std_logic;
  signal oder: std_logic;
  signal agb_b: boolean;
  signal aeb_b: boolean;
  
  begin
  -- Berechnung
  a_int <= unsigned(a);
  b_int <= unsigned(b);
  agb_b <= a_int > b_int;
  aeb_b <= std_match(a, b);
  inca <= std_logic_vector(a_int+1);
  add <= std_logic_vector(a_int+b_int);
  und <= a(0) and b(0);
  oder <= a(0) or b(0);
  shift <= std_logic_vector(shift_left(b_int,3));
  modulo <= std_logic_vector(a_int mod b_int);
  
  --Wertzuweisung potenzieller c's
  agb <= "0000001" when agb_b = true;
  aeb <= "0000001" when aeb_b = true;      
  
  
  with s select
    c <= agb when "000",
         aeb when "001",
         inca when "010",
         add when "011",
         "000000" & und when "100",
         "000000" & oder when "101",
         shift when "110",
         modulo when "111",
         "1111111" when others;
  
end arch;

The file are all named correctly. Altera Quartus II "Error (12061): Can't synthesize current design -- Top partition does not contain any logic" here it says something about a entity named correctly but I am not quite sure what exactly it is.

Your toplevel fpga_aufgabe1 does not have any output. So it does not contain any logic and obviously does nothing. — Matthias Schweikart, Apr 26 '23 at 17:06

score 0 · Answer 1 · answered Apr 27 '23 at 07:51

Your top level fpga_aufgabe1 has no outputs. Therefore it is a component without any observable effect, and the synthesizer optimizes all internal logic away.

A test bench as the top level has no inputs or outputs, and a simulator happily executes the statements inside it. You have at least one process with sequential steps, which resemble the tests you would do with the realized design.

Here we have the hint how to synthesize a design: The test bench commonly "embraces" the top level of the design, stimulates its inputs and checks its outputs.

For a successful synthesis you need a top level with at least one output. Add any input and output your FPGA design needs.

You can keep an abstract level here and use another small "wrapper" above this top level. This wrapper contains all the special components of the FPGA, which cannot be simulated, as clock modules, IO pin drivers, and so on. However, this wrapper should not have additional logic.

This figure shows an example:

Altera Quartus II Can't synthesize current design -- Top partition does not contain any logic

1 Answers1