In the following code, A
is attached to I/O while B
is an internal signal that is not assigned an initial value.
architecture Behavioral of adder is
signal B : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
process(clock)
variable result : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
if rising_edge(clock) then
result := STD_LOGIC_VECTOR(unsigned(A) + unsigned(B));
Y <= result;
B <= A;
end if;
end process;
end Behavioral;
If B is assigned after result is assigned, and B is not assigned until after the first pass, how will result be calculated?
In simulation, it shows 'X' for the output which is as expected, but how is this implemented in hardware?