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Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

180 questions
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Error: Cannot find buffer gate in the library

While attempting to synthesize with Yosys, I am unable to map the logic circuit using only AND, XOR, NOT, and MUX's. This is because I get an error whenever my liberty file excludes BUFX2: Error: ABC: ** cmd error: aborting 'source…
Mahmoud Maarouf
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Is it possible to use $display to print some values when proving with yosys-smtbmc?

In verilog $display() function is usefull in simulation to see the value of constants or macro like this example : /* Display parameters in simulation */ initial begin $display("CLK_PER_NS : %d", CLK_PER_NS ); $display("PULSE_PER_NS :…
FabienM
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Is there any alternative to (* keep *) in Verilog using ABC implementation?

I am using yosys to synthesize using the synth_ice40 command which calls ABC as well. In my Verilog code, I have used (* keep *) wire wire_1; Yosys does not optimize this but when it comes to ABC, it removes these unused wires. Is there anything…
qah
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Understanding Organization of the CRAM bits in bitstream .bin file

For an iCE40 1k device, Following is the snippet from the output of the command "iceunpack -vv example.bin" I could not understand why there are 332x144 bits? My understanding is that [1], the CRAM BLOCK[0] starts at the logic tile (1,1), and it…
Sajjad
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reading multiple block ram indexes in one write clock cycle

I have an application where I'm continuously writing to a block ram at a slow clock speed (clk_a) and within this slow clock cycle need to read three indexes from the block ram at a fast clock speed (clk_b) to use these values as operands in a math…
ke10g
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ice40 clock delay, output timing analysis

I have an ice40 that drives the clock and data inputs of an ASIC. The ice40 drives the ASIC's clock with the same clock that drives the ice40's internal logic. The problem is that the rising clock triggers the ice40's internal logic and changes the…
Dave
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What are PIP alternative in arachne-pnr?

While going through the router.cc the file of arcahne-pnr, I am unable to understand, how are the programmable interconnect pins PIPs routed? Does it seem PLL is representing the PIPs in the code? Could somebody help to make me clear, what…
qah
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Yosys ASIC synth flow QoR/PPA metrics

I'm relatively new to Yosys. I've been tinkering with it with some proprietary standard cell libraries and am trying to extract some QoR/PPA metrics, similar to those you can get from DC. Minimum slack (including worst-case negative slack/WNS) Max…
tedx
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Trouble getting YOSYS to infer block ram array (rather than using logic cells) verilog ice40

I've been having trouble the last little while with a project that uses look up table arrays quite a bit and getting yosys to infer them as block ram. Yosys keeps thinking one or the other of my arrays should be implemented using logic…
ke10g
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How to unpack LUTs into logic cells in verilog

I have a structural verilog containing LUTS all over him. I want this verilog to be unpacked so that I'll have the same functional but instead LUTS - I'll have logic cell (Like Or/And/Xor etc...). How can I do it ? Does Yosys has something built in…
yopsi
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Importing from Yosys, combinatorial logic directed graph into boost graph library

I want to import a large combinatorial logic circuit created in Yosys into a directed graph in my own c++ routines with boost graph library, so I can experiment with my own algorithms. The logic has on the order of 10M gates, so it's goal to have…
Anderson314159
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yosys synthesis- syntax error in for loop

I am trying to synthesize a verilog code that I have used a lot of for loops. However, I am getting syntax error due to using for loop. Take the following code as an example: integer j; always@(*)begin for(j = 0; j<3; j++) begin c[j]= c[j]…
M.X
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Yosys and Synplify compatible elements

I would like to write verilog that can be synthesized either using yosys (preferable) or the Lattice Radiant tool chain using Synplify (needed for encrypted IP from Lattice for example). Most of the hard cells like the PLL have different names…
Venkat
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Multiple conflicting drivers for reg assigned in only one always block

I'm working on a simple video signal timing module in Verilog, as a learning project. I've understood from earlier study that each reg should be assigned from only one always block, so I arranged my system into two state machine blocks and then one…
Martin Atkins
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Sub-module not found after changing parameter through chparam in a foreach loop

I am trying to synthesize a module for different values of a parameter. I am changing the parameter with a foreach loop in tcl and passing the updated parameter to the top module using -chparam tag in the hierarchy command. It works for the first…
Siam
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