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Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

180 questions
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Mapping of registers to gate level Verilog

I am using Yosys to synthesize an AES core to gate level Verilog with mapping to cells from a Liberty file. Is there a way to report the mapping of registers and memory instances from the RTL to the gate level instances/pins/nets? This is my…
David R.
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sequential equivalence with more than one multi bit register

extremely simple sequential logic equivalence test case: module memory1( input wire clk, input wire srst, input wire [15:0] addr, input wire din, input wire wr, input wire rd, …
turbo_fingers
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Segmentation fault: 11 while compiling with yosys

I'm trying to implement a Verilog module that writes in a Lattice UP5K SPRAM hardware core using the Yosys SB_SPRAM256KA block. Note that there are little or no documentation/examples about usage of this black box block. The main purpose is…
Pablo
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Characterization using YOSYS

Is there any way to obtain the Area, Energy Consumption or time delay of a mapped circuit using YOSYS? This is my synthesis script: read_verilog UBBKA_15_0_15_0.v hierarchy -top UBBKA_15_0_15_0 prep; flatten; synth clean -purge dfflibmap -liberty…
sudohumberto
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Yosys: Getting Gates /Transistor count

I am new to Yosys and synthesis but what I want to achieve is to get the number of gates and transistors after the design unit has undergone synthesis. How do I achieve that?
user2987773
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Simplify combinational logic using yosys

I am wondering if it is possible to use Yosys in simplifying logic equations. For example: module top ( output [31:0] cipher, input [31:0] plain, input [63:0] key ); wire tmp = key[31:0]; wire tmp2 = key[63:32] & 0; …
Xedar
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Strange RTL output

[Yosys 0.8] A colleague of mine threw some random verilog code to Yosys to see how it reacts. Here it is: module top(input clk, input led, output led2, output to_port1,output [24:0] to_port2); reg ctr = 0; reg[24:0] counter = 2; always@(posedge…
Larry
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How to use 'write_json' command in YosysJS

I am new to Yosys and trying to use YosysJS to generate a json description of an input verilog file. There is documentation on how to use the command in Yosys. But I do not understand how to use it in YosysJS. I can draw an RTL diagram after…
Aidar
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assume() does not work for initial statement

For https://i.imgur.com/NCUjYmr.png , why doesn't the signal "reset" assumed to be '1' initially ? Anyone have any idea why the assume does not work ?
kevin
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Reset behavior with miter equivalence checking

I'm trying to prove equivalence using miter and sat for a sequential circuit. Essentially, the behavior of the two circuits should be identical as soon as they are reset. I cannot figure out how to tell yosys this though. I have tried reseting the…
Jack Koenig
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is nested @ supported?

I am trying to create an implicit FSM using the following syntasix: always @(posedge clock) begin @(posedge clock)begin statement end @(posedge clock)begin statement end It works fine in simulation but when I try to…
sergicuen
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is it possible to change slew rate of pins with icestorm tools for the ice40 devices

I couldn't find any examples of pcf files setting slew or drive rates. I checked the tech paper that lists the io port primitives, and it seems possible to set the drive, but not the slew.
Matt Venn
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Manual manipulation of verilog connections

I am trying to use Yosys to implement post-synthesis manipulation of connections. i.e, I want to manually manipulate the connections between verilog modules after the synthesis pass is done. I tried investigating the code for a while, and I found…
AbdelAziz
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how to decompose a circuit into high-level modules

I am interested in taking a circuit, described in logic, and decomposing it into high-level connected modules, where each module say has 6 inputs and 5 outputs max. So it is similar to FPGAs in some sense except that the modules could have multiple…
S. Reda
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timing issues: simulation (iverilog, gtkwave) works, hardware (yosys) does not

I am learning verilog, trying do make the "hello world" in the VGA world (a bouncing ball) on a ice40LX1K board (olimex ice40HX1K + VGA I/O board). I have a strange problem: when I simulate my design using iverilog + GTKWave, it seams to work good.…
kristoff
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