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I am trying to synthesize a verilog code that I have used a lot of for loops. However, I am getting syntax error due to using for loop. Take the following code as an example:

integer j;
always@(*)begin
    for(j = 0; j<3; j++) begin
      c[j]= c[j] + 1;
    end
end

I tried to compile the code using iverilog and verilator and both of them compile it without error but yosys gives syntax error in line for(j = 0; j<3; j++) begin . Is there something I am missing when synthesizing with yosys?

I have uploaded a copy of this example code on edaplayground in following link: www.edaplayground.com/x/srL

Usman Khan
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M.X
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  • Strictly speaking, ++ is a SystemVerilog feature and earlier versions of Yosys didn't support it. However, latest Yosys does support it fine – gatecat Nov 11 '19 at 19:14
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    Thanks David. I just tried `j=j+1` instead of `j++` and it works now. Thanks – M.X Nov 12 '19 at 11:19
  • FWIW, Yosys 0.2 and 0.3 offered by edaplayground are very old versions now and I would strongly recommend either the 0.9 or latest git master – gatecat Nov 12 '19 at 11:46

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