I'm relatively new to Yosys. I've been tinkering with it with some proprietary standard cell libraries and am trying to extract some QoR/PPA metrics, similar to those you can get from DC.
- Minimum slack (including worst-case negative slack/WNS)
- Max logic depth [0]
- Cell area [1]
For [0], I know there's the ltp
command, but it only reports topological paths per module. I tried flattening the design using flatten
, but there still seems to be a hierarchy in the netlist. Where should I insert the flatten command to actually flatten the netlist?
For [1], I know you can get the number of cells in the netlist using the stat
command, but this doesn't tell me the equivalent of DC's CellArea metric (since each cell has a different area). I could just build a library of cell areas for each cell type based on the cell library datasheet, but that's rather laborious.
Also, is it possible to specify a target clock rate for synthesis? I think for abc
there was a -D
flag for delay, but this sounds to me more like input delay rather than clock period.
Thanks!